/[pcsx2_0.9.7]/trunk/plugins/SPU2null/SPU2.h
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Contents of /trunk/plugins/SPU2null/SPU2.h

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Revision 31 - (show annotations) (download)
Tue Sep 7 03:24:11 2010 UTC (10 years, 10 months ago) by william
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committing r3113 initial commit again...
1 /* SPU2null
2 * Copyright (C) 2002-2005 SPU2null Team
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */
18
19 #ifndef __SPU2_H__
20 #define __SPU2_H__
21
22 #define _CRT_SECURE_NO_DEPRECATE
23
24 #include <stdio.h>
25 #include <string.h>
26
27 extern "C"
28 {
29 #define SPU2defs
30 #include "PS2Edefs.h"
31 }
32
33 #ifdef __LINUX__
34 #include <gtk/gtk.h>
35 #else
36 #include <windows.h>
37 #include <windowsx.h>
38 #endif
39
40 #ifdef _MSC_VER
41 #define EXPORT_C_(type) extern "C" __declspec(dllexport) type CALLBACK
42 #else
43 #define EXPORT_C_(type) extern "C" type
44 #endif
45
46 extern FILE *spu2Log;
47 #define SPU2_LOG __Log //debug mode
48
49 extern const u8 version;
50 extern const u8 revision;
51 extern const u8 build;
52 extern const u32 minor;
53 extern char *libraryName;
54
55 typedef struct
56 {
57 s32 Log;
58 } Config;
59
60 extern Config conf;
61
62 void __Log(char *fmt, ...);
63 void SaveConfig();
64 void LoadConfig();
65 void SysMessage(char *fmt, ...);
66
67 ////////////////////
68 // SPU2 Registers //
69 ////////////////////
70 #define REG_VP_VOLL 0x0000
71 #define REG_VP_VOLR 0x0002
72 #define REG_VP_PITCH 0x0004
73 #define REG_VP_ADSR1 0x0006
74 #define REG_VP_ADSR2 0x0008
75 #define REG_VP_ENVX 0x000A
76 #define REG_VP_VOLXL 0x000C
77 #define REG_VP_VOLXR 0x000E
78 #define REG_C0_FMOD1 0x0180
79 #define REG_C0_FMOD2 0x0182
80 #define REG_C1_FMOD1 0x0580
81 #define REG_C1_FMOD2 0x0582
82 #define REG_S_NON 0x0184
83 #define REG_S_VMIXL 0x0188
84 #define REG_S_VMIXEL 0x018C
85 #define REG_S_VMIXR 0x0190
86 #define REG_S_VMIXER 0x0194
87 #define REG_C0_MMIX 0x0198
88 #define REG_C1_MMIX 0x0598
89 #define REG_C0_CTRL 0x019A
90 #define REG_C0_IRQA_HI 0x019C
91 #define REG_C0_IRQA_LO 0x019D
92 #define REG_C1_IRQA_HI 0x059C
93 #define REG_C1_IRQA_LO 0x059D
94 #define REG_C0_SPUON1 0x1A0
95 #define REG_C0_SPUON2 0x1A2
96 #define REG_C1_SPUON1 0x5A0
97 #define REG_C1_SPUON2 0x5A2
98 #define REG_C0_SPUOFF1 0x1A4
99 #define REG_C0_SPUOFF2 0x1A6
100 #define REG_C1_SPUOFF1 0x5A4
101 #define REG_C1_SPUOFF2 0x5A6
102 #define REG_C0_SPUADDR_HI 0x01A8
103 #define REG_C0_SPUADDR_LO 0x01AA
104 #define REG_C1_SPUADDR_HI 0x05A8
105 #define REG_C1_SPUADDR_LO 0x05AA
106 #define REG_C0_SPUDATA 0x01AC
107 #define REG_C1_SPUDATA 0x05AC
108 #define REG_C0_DMACTRL 0x01AE
109 #define REG_C1_DMACTRL 0x05AE
110 #define REG_C0_ADMAS 0x01B0
111 #define REG_VA_SSA 0x01C0
112 #define REG_VA_LSAX 0x01C4
113 #define REG_VA_NAX 0x01C8
114 #define REG_A_ESA 0x02E0
115 #define REG_A_EEA 0x033C
116 #define REG_C0_END1 0x0340
117 #define REG_C0_END2 0x0342
118 #define REG_C1_END1 0x0740
119 #define REG_C1_END2 0x0742
120 #define REG_C0_SPUSTAT 0x0344 //not sure!
121 #define REG_C1_CTRL 0x059A
122 #define REG_C1_ADMAS 0x05B0
123 #define REG_C1_SPUSTAT 0x0744 //not sure!
124 #define REG_P_MVOLL 0x0760
125 #define REG_P_MVOLR 0x0762
126 #define REG_P_EVOLL 0x0764
127 #define REG_P_EVOLR 0x0766
128 #define REG_P_AVOLL 0x0768
129 #define REG_P_AVOLR 0x076A
130 #define REG_P_BVOLL 0x076C
131 #define REG_P_BVOLR 0x076E
132 #define REG_P_MVOLXL 0x0770
133 #define REG_P_MVOLXR 0x0772
134 #define SPDIF_OUT 0x07C0
135 #define REG_IRQINFO 0x07C2
136 #define SPDIF_MODE 0x07C6
137 #define SPDIF_MEDIA 0x07C8
138
139 #define spu2Rs16(mem) (*(s16*)&spu2regs[(mem) & 0xffff])
140 #define spu2Ru16(mem) (*(u16*)&spu2regs[(mem) & 0xffff])
141 //#define spu2Rs32(mem) (*(s32*)&spu2regs[(mem) & 0xffff])
142 //#define spu2Ru32(mem) (*(u32*)&spu2regs[(mem) & 0xffff])
143
144 #define IRQINFO spu2Ru16(REG_IRQINFO)
145
146 #define SPU2_GET32BIT(lo,hi) (((u32)(spu2Ru16(hi)&0x3f)<<16)|(u32)spu2Ru16(lo))
147 #define SPU2_SET32BIT(value, lo, hi) { \
148 spu2Ru16(hi) = ((value)>>16)&0x3f; \
149 spu2Ru16(lo) = (value)&0xffff; \
150 } \
151
152 #define C0_IRQA SPU2_GET32BIT(REG_C0_IRQA_LO, REG_C0_IRQA_HI)
153 #define C1_IRQA SPU2_GET32BIT(REG_C1_IRQA_LO, REG_C1_IRQA_HI)
154
155 #define C0_SPUADDR SPU2_GET32BIT(REG_C0_SPUADDR_LO, REG_C0_SPUADDR_HI)
156 #define C1_SPUADDR SPU2_GET32BIT(REG_C1_SPUADDR_LO, REG_C1_SPUADDR_HI)
157
158 #define C0_SPUADDR_SET(value) SPU2_SET32BIT(value, REG_C0_IRQA_LO, REG_C0_IRQA_HI)
159 #define C1_SPUADDR_SET(value) SPU2_SET32BIT(value, REG_C1_IRQA_LO, REG_C1_IRQA_HI)
160
161 #define SPU_NUMBER_VOICES 48
162
163 struct SPU_CONTROL_
164 {
165 u16 spuon : 1;
166 u16 spuUnmute : 1;
167 u16 noiseFreq : 6;
168 u16 reverb : 1;
169 u16 irq : 1;
170 u16 dma : 2; // 1 - no dma, 2 - write, 3 - read
171 u16 extr : 1; // external reverb
172 u16 cdreverb : 1;
173 u16 extAudio : 1;
174 u16 extCd : 1;
175 };
176
177 // the layout of each voice in wSpuRegs
178 struct _SPU_VOICE
179 {
180 union
181 {
182 struct {
183 u16 Vol : 14;
184 u16 Inverted : 1;
185 u16 Sweep0 : 1;
186 } vol;
187 struct {
188 u16 Vol : 7;
189 u16 res1 : 5;
190 u16 Inverted : 1;
191 u16 Decrease : 1; // if 0, increase
192 u16 ExpSlope : 1; // if 0, linear slope
193 u16 Sweep1 : 1; // always one
194 } sweep;
195 u16 word;
196 } left, right;
197
198 u16 pitch : 14; // 1000 - no pitch, 2000 - pitch + 1, etc
199 u16 res0 : 2;
200
201 u16 SustainLvl : 4;
202 u16 DecayRate : 4;
203 u16 AttackRate : 7;
204 u16 AttackExp : 1; // if 0, linear
205
206 u16 ReleaseRate : 5;
207 u16 ReleaseExp : 1; // if 0, linear
208 u16 SustainRate : 7;
209 u16 res1 : 1;
210 u16 SustainDec : 1; // if 0, inc
211 u16 SustainExp : 1; // if 0, linear
212
213 u16 AdsrVol;
214 u16 Address; // add / 8
215 u16 RepeatAddr; // gets reset when sample starts
216 };
217
218 // ADSR INFOS PER CHANNEL
219 struct ADSRInfoEx
220 {
221 s32 State;
222 s32 AttackModeExp;
223 s32 AttackRate;
224 s32 DecayRate;
225 s32 SustainLevel;
226 s32 SustainModeExp;
227 s32 SustainIncrease;
228 s32 SustainRate;
229 s32 ReleaseModeExp;
230 s32 ReleaseRate;
231 s32 EnvelopeVol;
232 s32 lVolume;
233 };
234
235 #define NSSIZE 48 // ~ 1 ms of data
236 #define NSFRAMES 16 // gather at least NSFRAMES of NSSIZE before submitting
237 #define NSPACKETS 4
238 #define SPU_VOICE_STATE_SIZE (sizeof(VOICE_PROCESSED)-4*sizeof(void*))
239
240 struct VOICE_PROCESSED
241 {
242 VOICE_PROCESSED()
243 {
244 memset(this, 0, sizeof(VOICE_PROCESSED));
245 }
246 ~VOICE_PROCESSED()
247 {
248 }
249
250 void SetVolume(int right);
251 void StartSound();
252 void VoiceChangeFrequency();
253 void FModChangeFrequency(int ns);
254 void Stop();
255
256 SPU_CONTROL_* GetCtrl();
257
258 // start save state
259
260 s32 iSBPos; // mixing stuff
261 s32 spos;
262 s32 sinc;
263
264 s32 iActFreq; // current psx pitch
265 s32 iUsedFreq; // current pc pitch
266
267 s32 iStartAddr, iLoopAddr, iNextAddr;
268
269 ADSRInfoEx ADSRX; // next ADSR settings (will be moved to active on sample start)
270 bool bIgnoreLoop, bNew, bNoise, bReverb, bOn, bStop, bVolChanged;
271 s32 memoffset; // if first core, 0, if second, 0x400
272
273 // end save state
274
275 ///////////////////
276 // Sound Buffers //
277 ///////////////////
278 u8* pStart; // start and end addresses
279 u8* pLoop, *pCurr;
280
281 _SPU_VOICE* pvoice;
282 };
283
284 struct ADMA
285 {
286 u16 * MemAddr;
287 s32 IntPointer;
288 s32 Index;
289 s32 AmountLeft;
290 s32 Enabled;
291 };
292
293 #endif /* __SPU2_H__ */

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