/[pcsx2_0.9.7]/trunk/plugins/GSdx/GS.h
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Contents of /trunk/plugins/GSdx/GS.h

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Revision 280 - (show annotations) (download)
Thu Dec 23 12:02:12 2010 UTC (9 years, 2 months ago) by william
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re-commit (had local access denied errors when committing)
1 /*
2 * Copyright (C) 2007-2009 Gabest
3 * http://www.gabest.org
4 *
5 * This Program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2, or (at your option)
8 * any later version.
9 *
10 * This Program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with GNU Make; see the file COPYING. If not, write to
17 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
18 * http://www.gnu.org/copyleft/gpl.html
19 *
20 * Special Notes:
21 *
22 * Register definitions and most of the enums originate from sps2dev-0.4.0
23 * Copyright (C) 2002 Terratron Technologies Inc. All Rights Reserved.
24 *
25 */
26
27 #pragma once
28
29 #define PLUGIN_VERSION 16
30
31 #define MAX_PAGES 512
32 #define MAX_BLOCKS 16384
33
34 //if defined, will send much info in reply to the API title info queri from PCSX2
35 //default should be undefined
36 //#define GSTITLEINFO_API_FORCE_VERBOSE
37
38 #include "GSVector.h"
39
40 #pragma pack(push, 1)
41
42 //
43 // sps2registers.h
44 //
45
46 enum GS_PRIM
47 {
48 GS_POINTLIST = 0,
49 GS_LINELIST = 1,
50 GS_LINESTRIP = 2,
51 GS_TRIANGLELIST = 3,
52 GS_TRIANGLESTRIP = 4,
53 GS_TRIANGLEFAN = 5,
54 GS_SPRITE = 6,
55 GS_INVALID = 7,
56 };
57
58 enum GS_PRIM_CLASS
59 {
60 GS_POINT_CLASS = 0,
61 GS_LINE_CLASS = 1,
62 GS_TRIANGLE_CLASS = 2,
63 GS_SPRITE_CLASS = 3,
64 GS_INVALID_CLASS = 7,
65 };
66
67 enum GIF_REG
68 {
69 GIF_REG_PRIM = 0x00,
70 GIF_REG_RGBA = 0x01,
71 GIF_REG_STQ = 0x02,
72 GIF_REG_UV = 0x03,
73 GIF_REG_XYZF2 = 0x04,
74 GIF_REG_XYZ2 = 0x05,
75 GIF_REG_TEX0_1 = 0x06,
76 GIF_REG_TEX0_2 = 0x07,
77 GIF_REG_CLAMP_1 = 0x08,
78 GIF_REG_CLAMP_2 = 0x09,
79 GIF_REG_FOG = 0x0a,
80 GIF_REG_XYZF3 = 0x0c,
81 GIF_REG_XYZ3 = 0x0d,
82 GIF_REG_A_D = 0x0e,
83 GIF_REG_NOP = 0x0f,
84 };
85
86 enum GIF_A_D_REG
87 {
88 GIF_A_D_REG_PRIM = 0x00,
89 GIF_A_D_REG_RGBAQ = 0x01,
90 GIF_A_D_REG_ST = 0x02,
91 GIF_A_D_REG_UV = 0x03,
92 GIF_A_D_REG_XYZF2 = 0x04,
93 GIF_A_D_REG_XYZ2 = 0x05,
94 GIF_A_D_REG_TEX0_1 = 0x06,
95 GIF_A_D_REG_TEX0_2 = 0x07,
96 GIF_A_D_REG_CLAMP_1 = 0x08,
97 GIF_A_D_REG_CLAMP_2 = 0x09,
98 GIF_A_D_REG_FOG = 0x0a,
99 GIF_A_D_REG_XYZF3 = 0x0c,
100 GIF_A_D_REG_XYZ3 = 0x0d,
101 GIF_A_D_REG_NOP = 0x0f,
102 GIF_A_D_REG_TEX1_1 = 0x14,
103 GIF_A_D_REG_TEX1_2 = 0x15,
104 GIF_A_D_REG_TEX2_1 = 0x16,
105 GIF_A_D_REG_TEX2_2 = 0x17,
106 GIF_A_D_REG_XYOFFSET_1 = 0x18,
107 GIF_A_D_REG_XYOFFSET_2 = 0x19,
108 GIF_A_D_REG_PRMODECONT = 0x1a,
109 GIF_A_D_REG_PRMODE = 0x1b,
110 GIF_A_D_REG_TEXCLUT = 0x1c,
111 GIF_A_D_REG_SCANMSK = 0x22,
112 GIF_A_D_REG_MIPTBP1_1 = 0x34,
113 GIF_A_D_REG_MIPTBP1_2 = 0x35,
114 GIF_A_D_REG_MIPTBP2_1 = 0x36,
115 GIF_A_D_REG_MIPTBP2_2 = 0x37,
116 GIF_A_D_REG_TEXA = 0x3b,
117 GIF_A_D_REG_FOGCOL = 0x3d,
118 GIF_A_D_REG_TEXFLUSH = 0x3f,
119 GIF_A_D_REG_SCISSOR_1 = 0x40,
120 GIF_A_D_REG_SCISSOR_2 = 0x41,
121 GIF_A_D_REG_ALPHA_1 = 0x42,
122 GIF_A_D_REG_ALPHA_2 = 0x43,
123 GIF_A_D_REG_DIMX = 0x44,
124 GIF_A_D_REG_DTHE = 0x45,
125 GIF_A_D_REG_COLCLAMP = 0x46,
126 GIF_A_D_REG_TEST_1 = 0x47,
127 GIF_A_D_REG_TEST_2 = 0x48,
128 GIF_A_D_REG_PABE = 0x49,
129 GIF_A_D_REG_FBA_1 = 0x4a,
130 GIF_A_D_REG_FBA_2 = 0x4b,
131 GIF_A_D_REG_FRAME_1 = 0x4c,
132 GIF_A_D_REG_FRAME_2 = 0x4d,
133 GIF_A_D_REG_ZBUF_1 = 0x4e,
134 GIF_A_D_REG_ZBUF_2 = 0x4f,
135 GIF_A_D_REG_BITBLTBUF = 0x50,
136 GIF_A_D_REG_TRXPOS = 0x51,
137 GIF_A_D_REG_TRXREG = 0x52,
138 GIF_A_D_REG_TRXDIR = 0x53,
139 GIF_A_D_REG_HWREG = 0x54,
140 GIF_A_D_REG_SIGNAL = 0x60,
141 GIF_A_D_REG_FINISH = 0x61,
142 GIF_A_D_REG_LABEL = 0x62,
143 };
144
145 enum GIF_FLG
146 {
147 GIF_FLG_PACKED = 0,
148 GIF_FLG_REGLIST = 1,
149 GIF_FLG_IMAGE = 2,
150 GIF_FLG_IMAGE2 = 3
151 };
152
153 enum GS_PSM
154 {
155 PSM_PSMCT32 = 0, // 0000-0000
156 PSM_PSMCT24 = 1, // 0000-0001
157 PSM_PSMCT16 = 2, // 0000-0010
158 PSM_PSMCT16S = 10, // 0000-1010
159 PSM_PSMT8 = 19, // 0001-0011
160 PSM_PSMT4 = 20, // 0001-0100
161 PSM_PSMT8H = 27, // 0001-1011
162 PSM_PSMT4HL = 36, // 0010-0100
163 PSM_PSMT4HH = 44, // 0010-1100
164 PSM_PSMZ32 = 48, // 0011-0000
165 PSM_PSMZ24 = 49, // 0011-0001
166 PSM_PSMZ16 = 50, // 0011-0010
167 PSM_PSMZ16S = 58, // 0011-1010
168 };
169
170 enum GS_TFX
171 {
172 TFX_MODULATE = 0,
173 TFX_DECAL = 1,
174 TFX_HIGHLIGHT = 2,
175 TFX_HIGHLIGHT2 = 3,
176 TFX_NONE = 4,
177 };
178
179 enum GS_CLAMP
180 {
181 CLAMP_REPEAT = 0,
182 CLAMP_CLAMP = 1,
183 CLAMP_REGION_CLAMP = 2,
184 CLAMP_REGION_REPEAT = 3,
185 };
186
187 enum GS_ZTST
188 {
189 ZTST_NEVER = 0,
190 ZTST_ALWAYS = 1,
191 ZTST_GEQUAL = 2,
192 ZTST_GREATER = 3,
193 };
194
195 enum GS_ATST
196 {
197 ATST_NEVER = 0,
198 ATST_ALWAYS = 1,
199 ATST_LESS = 2,
200 ATST_LEQUAL = 3,
201 ATST_EQUAL = 4,
202 ATST_GEQUAL = 5,
203 ATST_GREATER = 6,
204 ATST_NOTEQUAL = 7,
205 };
206
207 enum GS_AFAIL
208 {
209 AFAIL_KEEP = 0,
210 AFAIL_FB_ONLY = 1,
211 AFAIL_ZB_ONLY = 2,
212 AFAIL_RGB_ONLY = 3,
213 };
214
215 //
216 // sps2regstructs.h
217 //
218
219 #define REG32(name) \
220 union name \
221 { \
222 uint32 u32; \
223 struct { \
224
225 #define REG64(name) \
226 union name \
227 { \
228 uint64 u64; \
229 uint32 u32[2]; \
230 void operator = (const GSVector4i& v) {GSVector4i::storel(this, v);} \
231 bool operator == (const union name& r) const {return ((GSVector4i)r).eq(*this);} \
232 bool operator != (const union name& r) const {return !((GSVector4i)r).eq(*this);} \
233 operator GSVector4i() const {return GSVector4i::loadl(this);} \
234 struct { \
235
236 #define REG128(name)\
237 union name \
238 { \
239 uint64 u64[2]; \
240 uint32 u32[4]; \
241 struct { \
242
243 #define REG32_(prefix, name) REG32(prefix##name)
244 #define REG64_(prefix, name) REG64(prefix##name)
245 #define REG128_(prefix, name) REG128(prefix##name)
246
247 #define REG_END }; };
248 #define REG_END2 };
249
250 #define REG32_SET(name) \
251 union name \
252 { \
253 uint32 u32; \
254
255 #define REG64_SET(name) \
256 union name \
257 { \
258 uint64 u64; \
259 uint32 u32[2]; \
260
261 #define REG128_SET(name)\
262 union name \
263 { \
264 __m128i m128; \
265 uint64 u64[2]; \
266 uint32 u32[4]; \
267
268 #define REG_SET_END };
269
270 REG64_(GSReg, BGCOLOR)
271 uint8 R;
272 uint8 G;
273 uint8 B;
274 uint8 _PAD1[5];
275 REG_END
276
277 REG64_(GSReg, BUSDIR)
278 uint32 DIR:1;
279 uint32 _PAD1:31;
280 uint32 _PAD2:32;
281 REG_END
282
283 REG64_(GSReg, CSR)
284 uint32 rSIGNAL:1;
285 uint32 rFINISH:1;
286 uint32 rHSINT:1;
287 uint32 rVSINT:1;
288 uint32 rEDWINT:1;
289 uint32 rZERO1:1;
290 uint32 rZERO2:1;
291 uint32 r_PAD1:1;
292 uint32 rFLUSH:1;
293 uint32 rRESET:1;
294 uint32 r_PAD2:2;
295 uint32 rNFIELD:1;
296 uint32 rFIELD:1;
297 uint32 rFIFO:2;
298 uint32 rREV:8;
299 uint32 rID:8;
300 uint32 wSIGNAL:1;
301 uint32 wFINISH:1;
302 uint32 wHSINT:1;
303 uint32 wVSINT:1;
304 uint32 wEDWINT:1;
305 uint32 wZERO1:1;
306 uint32 wZERO2:1;
307 uint32 w_PAD1:1;
308 uint32 wFLUSH:1;
309 uint32 wRESET:1;
310 uint32 w_PAD2:2;
311 uint32 wNFIELD:1;
312 uint32 wFIELD:1;
313 uint32 wFIFO:2;
314 uint32 wREV:8;
315 uint32 wID:8;
316 REG_END
317
318 REG64_(GSReg, DISPFB) // (-1/2)
319 uint32 FBP:9;
320 uint32 FBW:6;
321 uint32 PSM:5;
322 uint32 _PAD:12;
323 uint32 DBX:11;
324 uint32 DBY:11;
325 uint32 _PAD2:10;
326 REG_END2
327 uint32 Block() const {return FBP << 5;}
328 REG_END2
329
330 REG64_(GSReg, DISPLAY) // (-1/2)
331 uint32 DX:12;
332 uint32 DY:11;
333 uint32 MAGH:4;
334 uint32 MAGV:2;
335 uint32 _PAD:3;
336 uint32 DW:12;
337 uint32 DH:11;
338 uint32 _PAD2:9;
339 REG_END
340
341 REG64_(GSReg, EXTBUF)
342 uint32 EXBP:14;
343 uint32 EXBW:6;
344 uint32 FBIN:2;
345 uint32 WFFMD:1;
346 uint32 EMODA:2;
347 uint32 EMODC:2;
348 uint32 _PAD1:5;
349 uint32 WDX:11;
350 uint32 WDY:11;
351 uint32 _PAD2:10;
352 REG_END
353
354 REG64_(GSReg, EXTDATA)
355 uint32 SX:12;
356 uint32 SY:11;
357 uint32 SMPH:4;
358 uint32 SMPV:2;
359 uint32 _PAD1:3;
360 uint32 WW:12;
361 uint32 WH:11;
362 uint32 _PAD2:9;
363 REG_END
364
365 REG64_(GSReg, EXTWRITE)
366 uint32 WRITE:1;
367 uint32 _PAD1:31;
368 uint32 _PAD2:32;
369 REG_END
370
371 REG64_(GSReg, IMR)
372 uint32 _PAD1:8;
373 uint32 SIGMSK:1;
374 uint32 FINISHMSK:1;
375 uint32 HSMSK:1;
376 uint32 VSMSK:1;
377 uint32 EDWMSK:1;
378 uint32 _PAD2:19;
379 uint32 _PAD3:32;
380 REG_END
381
382 REG64_(GSReg, PMODE)
383 union
384 {
385 struct
386 {
387 uint32 EN1:1;
388 uint32 EN2:1;
389 uint32 CRTMD:3;
390 uint32 MMOD:1;
391 uint32 AMOD:1;
392 uint32 SLBG:1;
393 uint32 ALP:8;
394 uint32 _PAD:16;
395 uint32 _PAD1:32;
396 };
397
398 struct
399 {
400 uint32 EN:2;
401 uint32 _PAD2:30;
402 uint32 _PAD3:32;
403 };
404 };
405 REG_END
406
407 REG64_(GSReg, SIGLBLID)
408 uint32 SIGID;
409 uint32 LBLID;
410 REG_END
411
412 REG64_(GSReg, SMODE1)
413 uint32 RC:3;
414 uint32 LC:7;
415 uint32 T1248:2;
416 uint32 SLCK:1;
417 uint32 CMOD:2;
418 uint32 EX:1;
419 uint32 PRST:1;
420 uint32 SINT:1;
421 uint32 XPCK:1;
422 uint32 PCK2:2;
423 uint32 SPML:4;
424 uint32 GCONT:1; // YCrCb
425 uint32 PHS:1;
426 uint32 PVS:1;
427 uint32 PEHS:1;
428 uint32 PEVS:1;
429 uint32 CLKSEL:2;
430 uint32 NVCK:1;
431 uint32 SLCK2:1;
432 uint32 VCKSEL:2;
433 uint32 VHP:1;
434 uint32 _PAD1:27;
435 REG_END
436
437 /*
438
439 // pal
440
441 CLKSEL=1 CMOD=3 EX=0 GCONT=0 LC=32 NVCK=1 PCK2=0 PEHS=0 PEVS=0 PHS=0 PRST=1 PVS=0 RC=4 SINT=0 SLCK=0 SLCK2=1 SPML=4 T1248=1 VCKSEL=1 VHP=0 XPCK=0
442
443 // ntsc
444
445 CLKSEL=1 CMOD=2 EX=0 GCONT=0 LC=32 NVCK=1 PCK2=0 PEHS=0 PEVS=0 PHS=0 PRST=1 PVS=0 RC=4 SINT=0 SLCK=0 SLCK2=1 SPML=4 T1248=1 VCKSEL=1 VHP=0 XPCK=0
446
447 // ntsc progressive (SoTC)
448
449 CLKSEL=1 CMOD=0 EX=0 GCONT=0 LC=32 NVCK=1 PCK2=0 PEHS=0 PEVS=0 PHS=0 PRST=1 PVS=0 RC=4 SINT=0 SLCK=0 SLCK2=1 SPML=2 T1248=1 VCKSEL=1 VHP=1 XPCK=0
450
451 */
452
453 REG64_(GSReg, SMODE2)
454 uint32 INT:1;
455 uint32 FFMD:1;
456 uint32 DPMS:2;
457 uint32 _PAD2:28;
458 uint32 _PAD3:32;
459 REG_END
460
461 REG64_(GSReg, SRFSH)
462 uint32 _DUMMY;
463 // TODO
464 REG_END
465
466 REG64_(GSReg, SYNCH1)
467 uint32 _DUMMY;
468 // TODO
469 REG_END
470
471 REG64_(GSReg, SYNCH2)
472 uint32 _DUMMY;
473 // TODO
474 REG_END
475
476 REG64_(GSReg, SYNCV)
477 uint64 _DUMMY;
478 // TODO
479 REG_END
480
481 REG64_SET(GSReg)
482 GSRegBGCOLOR BGCOLOR;
483 GSRegBUSDIR BUSDIR;
484 GSRegCSR CSR;
485 GSRegDISPFB DISPFB;
486 GSRegDISPLAY DISPLAY;
487 GSRegEXTBUF EXTBUF;
488 GSRegEXTDATA EXTDATA;
489 GSRegEXTWRITE EXTWRITE;
490 GSRegIMR IMR;
491 GSRegPMODE PMODE;
492 GSRegSIGLBLID SIGLBLID;
493 GSRegSMODE1 SMODE1;
494 GSRegSMODE2 SMODE2;
495 REG_SET_END
496
497 //
498 // sps2tags.h
499 //
500
501 #define SET_GIF_REG(gifTag, iRegNo, uiValue) \
502 {((GIFTag*)&gifTag)->u64[1] |= (((uiValue) & 0xf) << ((iRegNo) << 2));}
503
504 #ifdef _M_AMD64
505 #define GET_GIF_REG(tag, reg) \
506 (((tag).u64[1] >> ((reg) << 2)) & 0xf)
507 #else
508 #define GET_GIF_REG(tag, reg) \
509 (((tag).u32[2 + ((reg) >> 3)] >> (((reg) & 7) << 2)) & 0xf)
510 #endif
511
512 //
513 // GIFTag
514
515 REG128(GIFTag)
516 uint32 NLOOP:15;
517 uint32 EOP:1;
518 uint32 _PAD1:16;
519 uint32 _PAD2:14;
520 uint32 PRE:1;
521 uint32 PRIM:11;
522 uint32 FLG:2; // enum GIF_FLG
523 uint32 NREG:4;
524 uint64 REGS;
525 REG_END
526
527 // GIFReg
528
529 REG64_(GIFReg, ALPHA)
530 uint32 A:2;
531 uint32 B:2;
532 uint32 C:2;
533 uint32 D:2;
534 uint32 _PAD1:24;
535 uint8 FIX;
536 uint8 _PAD2[3];
537 REG_END2
538 // opaque => output will be Cs/As
539 __forceinline bool IsOpaque() const {return (A == B || C == 2 && FIX == 0) && D == 0 || (A == 0 && B == D && C == 2 && FIX == 0x80);}
540 __forceinline bool IsOpaque(int amin, int amax) const {return (A == B || amax == 0) && D == 0 || A == 0 && B == D && amin == 0x80 && amax == 0x80;}
541 REG_END2
542
543 REG64_(GIFReg, BITBLTBUF)
544 uint32 SBP:14;
545 uint32 _PAD1:2;
546 uint32 SBW:6;
547 uint32 _PAD2:2;
548 uint32 SPSM:6;
549 uint32 _PAD3:2;
550 uint32 DBP:14;
551 uint32 _PAD4:2;
552 uint32 DBW:6;
553 uint32 _PAD5:2;
554 uint32 DPSM:6;
555 uint32 _PAD6:2;
556 REG_END
557
558 REG64_(GIFReg, CLAMP)
559 union
560 {
561 struct
562 {
563 uint32 WMS:2;
564 uint32 WMT:2;
565 uint32 MINU:10;
566 uint32 MAXU:10;
567 uint32 _PAD1:8;
568 uint32 _PAD2:2;
569 uint32 MAXV:10;
570 uint32 _PAD3:20;
571 };
572
573 struct
574 {
575 uint64 _PAD4:24;
576 uint64 MINV:10;
577 uint64 _PAD5:30;
578 };
579 };
580 REG_END
581
582 REG64_(GIFReg, COLCLAMP)
583 uint32 CLAMP:1;
584 uint32 _PAD1:31;
585 uint32 _PAD2:32;
586 REG_END
587
588 REG64_(GIFReg, DIMX)
589 int32 DM00:3;
590 int32 _PAD00:1;
591 int32 DM01:3;
592 int32 _PAD01:1;
593 int32 DM02:3;
594 int32 _PAD02:1;
595 int32 DM03:3;
596 int32 _PAD03:1;
597 int32 DM10:3;
598 int32 _PAD10:1;
599 int32 DM11:3;
600 int32 _PAD11:1;
601 int32 DM12:3;
602 int32 _PAD12:1;
603 int32 DM13:3;
604 int32 _PAD13:1;
605 int32 DM20:3;
606 int32 _PAD20:1;
607 int32 DM21:3;
608 int32 _PAD21:1;
609 int32 DM22:3;
610 int32 _PAD22:1;
611 int32 DM23:3;
612 int32 _PAD23:1;
613 int32 DM30:3;
614 int32 _PAD30:1;
615 int32 DM31:3;
616 int32 _PAD31:1;
617 int32 DM32:3;
618 int32 _PAD32:1;
619 int32 DM33:3;
620 int32 _PAD33:1;
621 REG_END
622
623 REG64_(GIFReg, DTHE)
624 uint32 DTHE:1;
625 uint32 _PAD1:31;
626 uint32 _PAD2:32;
627 REG_END
628
629 REG64_(GIFReg, FBA)
630 uint32 FBA:1;
631 uint32 _PAD1:31;
632 uint32 _PAD2:32;
633 REG_END
634
635 REG64_(GIFReg, FINISH)
636 uint32 _PAD1[2];
637 REG_END
638
639 REG64_(GIFReg, FOG)
640 uint8 _PAD1[4+3];
641 uint8 F:8;
642 REG_END
643
644 REG64_(GIFReg, FOGCOL)
645 uint8 FCR;
646 uint8 FCG;
647 uint8 FCB;
648 uint8 _PAD1[5];
649 REG_END
650
651 REG64_(GIFReg, FRAME)
652 uint32 FBP:9;
653 uint32 _PAD1:7;
654 uint32 FBW:6;
655 uint32 _PAD2:2;
656 uint32 PSM:6;
657 uint32 _PAD3:2;
658 uint32 FBMSK;
659 REG_END2
660 uint32 Block() const {return FBP << 5;}
661 REG_END2
662
663 REG64_(GIFReg, HWREG)
664 uint32 DATA_LOWER;
665 uint32 DATA_UPPER;
666 REG_END
667
668 REG64_(GIFReg, LABEL)
669 uint32 ID;
670 uint32 IDMSK;
671 REG_END
672
673 REG64_(GIFReg, MIPTBP1)
674 uint64 TBP1:14;
675 uint64 TBW1:6;
676 uint64 TBP2:14;
677 uint64 TBW2:6;
678 uint64 TBP3:14;
679 uint64 TBW3:6;
680 uint64 _PAD:4;
681 REG_END
682
683 REG64_(GIFReg, MIPTBP2)
684 uint64 TBP4:14;
685 uint64 TBW4:6;
686 uint64 TBP5:14;
687 uint64 TBW5:6;
688 uint64 TBP6:14;
689 uint64 TBW6:6;
690 uint64 _PAD:4;
691 REG_END
692
693 REG64_(GIFReg, NOP)
694 uint32 _PAD[2];
695 REG_END
696
697 REG64_(GIFReg, PABE)
698 uint32 PABE:1;
699 uint32 _PAD1:31;
700 uint32 _PAD2:32;
701 REG_END
702
703 REG64_(GIFReg, PRIM)
704 uint32 PRIM:3;
705 uint32 IIP:1;
706 uint32 TME:1;
707 uint32 FGE:1;
708 uint32 ABE:1;
709 uint32 AA1:1;
710 uint32 FST:1;
711 uint32 CTXT:1;
712 uint32 FIX:1;
713 uint32 _PAD1:21;
714 uint32 _PAD2:32;
715 REG_END
716
717 REG64_(GIFReg, PRMODE)
718 uint32 _PRIM:3;
719 uint32 IIP:1;
720 uint32 TME:1;
721 uint32 FGE:1;
722 uint32 ABE:1;
723 uint32 AA1:1;
724 uint32 FST:1;
725 uint32 CTXT:1;
726 uint32 FIX:1;
727 uint32 _PAD2:21;
728 uint32 _PAD3:32;
729 REG_END
730
731 REG64_(GIFReg, PRMODECONT)
732 uint32 AC:1;
733 uint32 _PAD1:31;
734 uint32 _PAD2:32;
735 REG_END
736
737 REG64_(GIFReg, RGBAQ)
738 uint8 R;
739 uint8 G;
740 uint8 B;
741 uint8 A;
742 float Q;
743 REG_END
744
745 REG64_(GIFReg, SCANMSK)
746 uint32 MSK:2;
747 uint32 _PAD1:30;
748 uint32 _PAD2:32;
749 REG_END
750
751 REG64_(GIFReg, SCISSOR)
752 uint32 SCAX0:11;
753 uint32 _PAD1:5;
754 uint32 SCAX1:11;
755 uint32 _PAD2:5;
756 uint32 SCAY0:11;
757 uint32 _PAD3:5;
758 uint32 SCAY1:11;
759 uint32 _PAD4:5;
760 REG_END
761
762 REG64_(GIFReg, SIGNAL)
763 uint32 ID;
764 uint32 IDMSK;
765 REG_END
766
767 REG64_(GIFReg, ST)
768 float S;
769 float T;
770 REG_END
771
772 REG64_(GIFReg, TEST)
773 uint32 ATE:1;
774 uint32 ATST:3;
775 uint32 AREF:8;
776 uint32 AFAIL:2;
777 uint32 DATE:1;
778 uint32 DATM:1;
779 uint32 ZTE:1;
780 uint32 ZTST:2;
781 uint32 _PAD1:13;
782 uint32 _PAD2:32;
783 REG_END2
784 __forceinline bool DoFirstPass() {return !ATE || ATST != ATST_NEVER;} // not all pixels fail automatically
785 __forceinline bool DoSecondPass() {return ATE && ATST != ATST_ALWAYS && AFAIL != AFAIL_KEEP;} // pixels may fail, write fb/z
786 __forceinline bool NoSecondPass() {return ATE && ATST != ATST_ALWAYS && AFAIL == AFAIL_KEEP;} // pixels may fail, no output
787 REG_END2
788
789 REG64_(GIFReg, TEX0)
790 union
791 {
792 struct
793 {
794 uint32 TBP0:14;
795 uint32 TBW:6;
796 uint32 PSM:6;
797 uint32 TW:4;
798 uint32 _PAD1:2;
799 uint32 _PAD2:2;
800 uint32 TCC:1;
801 uint32 TFX:2;
802 uint32 CBP:14;
803 uint32 CPSM:4;
804 uint32 CSM:1;
805 uint32 CSA:5;
806 uint32 CLD:3;
807 };
808
809 struct
810 {
811 uint64 _PAD3:30;
812 uint64 TH:4;
813 uint64 _PAD4:30;
814 };
815 };
816 REG_END2
817 __forceinline bool IsRepeating() {return ((uint32)1 << TW) > (TBW << 6);}
818 REG_END2
819
820 REG64_(GIFReg, TEX1)
821 uint32 LCM:1;
822 uint32 _PAD1:1;
823 uint32 MXL:3;
824 uint32 MMAG:1;
825 uint32 MMIN:3;
826 uint32 MTBA:1;
827 uint32 _PAD2:9;
828 uint32 L:2;
829 uint32 _PAD3:11;
830 int32 K:12; // 1:7:4
831 uint32 _PAD4:20;
832 REG_END2
833 bool IsMinLinear() const {return (MMIN == 1) || (MMIN & 4);}
834 bool IsMagLinear() const {return MMAG;}
835 REG_END2
836
837 REG64_(GIFReg, TEX2)
838 uint32 _PAD1:20;
839 uint32 PSM:6;
840 uint32 _PAD2:6;
841 uint32 _PAD3:5;
842 uint32 CBP:14;
843 uint32 CPSM:4;
844 uint32 CSM:1;
845 uint32 CSA:5;
846 uint32 CLD:3;
847 REG_END
848
849 REG64_(GIFReg, TEXA)
850 uint8 TA0;
851 uint8 _PAD1:7;
852 uint8 AEM:1;
853 uint16 _PAD2;
854 uint8 TA1:8;
855 uint8 _PAD3[3];
856 REG_END
857
858 REG64_(GIFReg, TEXCLUT)
859 uint32 CBW:6;
860 uint32 COU:6;
861 uint32 COV:10;
862 uint32 _PAD1:10;
863 uint32 _PAD2:32;
864 REG_END
865
866 REG64_(GIFReg, TEXFLUSH)
867 uint32 _PAD1:32;
868 uint32 _PAD2:32;
869 REG_END
870
871 REG64_(GIFReg, TRXDIR)
872 uint32 XDIR:2;
873 uint32 _PAD1:30;
874 uint32 _PAD2:32;
875 REG_END
876
877 REG64_(GIFReg, TRXPOS)
878 uint32 SSAX:11;
879 uint32 _PAD1:5;
880 uint32 SSAY:11;
881 uint32 _PAD2:5;
882 uint32 DSAX:11;
883 uint32 _PAD3:5;
884 uint32 DSAY:11;
885 uint32 DIRY:1;
886 uint32 DIRX:1;
887 uint32 _PAD4:3;
888 REG_END
889
890 REG64_(GIFReg, TRXREG)
891 uint32 RRW:12;
892 uint32 _PAD1:20;
893 uint32 RRH:12;
894 uint32 _PAD2:20;
895 REG_END
896
897 // GSState::GIFPackedRegHandlerUV and GSState::GIFRegHandlerUV will make sure that the _PAD1/2 bits are set to zero
898
899 REG64_(GIFReg, UV)
900 uint16 U;
901 // uint32 _PAD1:2;
902 uint16 V;
903 // uint32 _PAD2:2;
904 uint32 _PAD3;
905 REG_END
906
907 // GSState::GIFRegHandlerXYOFFSET will make sure that the _PAD1/2 bits are set to zero
908
909 REG64_(GIFReg, XYOFFSET)
910 uint32 OFX; // :16; uint32 _PAD1:16;
911 uint32 OFY; // :16; uint32 _PAD2:16;
912 REG_END
913
914 REG64_(GIFReg, XYZ)
915 uint16 X;
916 uint16 Y;
917 uint32 Z;
918 REG_END
919
920 REG64_(GIFReg, XYZF)
921 uint16 X;
922 uint16 Y;
923 uint32 Z:24;
924 uint32 F:8;
925 REG_END
926
927 REG64_(GIFReg, ZBUF)
928 uint32 ZBP:9;
929 uint32 _PAD1:15;
930 // uint32 PSM:4;
931 // uint32 _PAD2:4;
932 uint32 PSM:6;
933 uint32 _PAD2:2;
934 uint32 ZMSK:1;
935 uint32 _PAD3:31;
936 REG_END2
937 uint32 Block() const {return ZBP << 5;}
938 REG_END2
939
940 REG64_SET(GIFReg)
941 GIFRegALPHA ALPHA;
942 GIFRegBITBLTBUF BITBLTBUF;
943 GIFRegCLAMP CLAMP;
944 GIFRegCOLCLAMP COLCLAMP;
945 GIFRegDIMX DIMX;
946 GIFRegDTHE DTHE;
947 GIFRegFBA FBA;
948 GIFRegFINISH FINISH;
949 GIFRegFOG FOG;
950 GIFRegFOGCOL FOGCOL;
951 GIFRegFRAME FRAME;
952 GIFRegHWREG HWREG;
953 GIFRegLABEL LABEL;
954 GIFRegMIPTBP1 MIPTBP1;
955 GIFRegMIPTBP2 MIPTBP2;
956 GIFRegNOP NOP;
957 GIFRegPABE PABE;
958 GIFRegPRIM PRIM;
959 GIFRegPRMODE PRMODE;
960 GIFRegPRMODECONT PRMODECONT;
961 GIFRegRGBAQ RGBAQ;
962 GIFRegSCANMSK SCANMSK;
963 GIFRegSCISSOR SCISSOR;
964 GIFRegSIGNAL SIGNAL;
965 GIFRegST ST;
966 GIFRegTEST TEST;
967 GIFRegTEX0 TEX0;
968 GIFRegTEX1 TEX1;
969 GIFRegTEX2 TEX2;
970 GIFRegTEXA TEXA;
971 GIFRegTEXCLUT TEXCLUT;
972 GIFRegTEXFLUSH TEXFLUSH;
973 GIFRegTRXDIR TRXDIR;
974 GIFRegTRXPOS TRXPOS;
975 GIFRegTRXREG TRXREG;
976 GIFRegUV UV;
977 GIFRegXYOFFSET XYOFFSET;
978 GIFRegXYZ XYZ;
979 GIFRegXYZF XYZF;
980 GIFRegZBUF ZBUF;
981 REG_SET_END
982
983 // GIFPacked
984
985 REG128_(GIFPacked, PRIM)
986 uint32 PRIM:11;
987 uint32 _PAD1:21;
988 uint32 _PAD2[3];
989 REG_END
990
991 REG128_(GIFPacked, RGBA)
992 uint8 R;
993 uint8 _PAD1[3];
994 uint8 G;
995 uint8 _PAD2[3];
996 uint8 B;
997 uint8 _PAD3[3];
998 uint8 A;
999 uint8 _PAD4[3];
1000 REG_END
1001
1002 REG128_(GIFPacked, STQ)
1003 float S;
1004 float T;
1005 float Q;
1006 uint32 _PAD1:32;
1007 REG_END
1008
1009 REG128_(GIFPacked, UV)
1010 uint32 U:14;
1011 uint32 _PAD1:18;
1012 uint32 V:14;
1013 uint32 _PAD2:18;
1014 uint32 _PAD3:32;
1015 uint32 _PAD4:32;
1016 REG_END
1017
1018 REG128_(GIFPacked, XYZF2)
1019 uint16 X;
1020 uint16 _PAD1;
1021 uint16 Y;
1022 uint16 _PAD2;
1023
1024 uint32 _PAD3:4;
1025 uint32 Z:24;
1026 uint32 _PAD4:4;
1027 uint32 _PAD5:4;
1028 uint32 F:8;
1029 uint32 _PAD6:3;
1030 uint32 ADC:1;
1031 uint32 _PAD7:16;
1032 REG_END
1033
1034 REG128_(GIFPacked, XYZ2)
1035 uint16 X;
1036 uint16 _PAD1;
1037 uint16 Y;
1038 uint16 _PAD2;
1039 uint32 Z;
1040 uint32 _PAD3:15;
1041 uint32 ADC:1;
1042 uint32 _PAD4:16;
1043 REG_END
1044
1045 REG128_(GIFPacked, FOG)
1046 uint32 _PAD1;
1047 uint32 _PAD2;
1048 uint32 _PAD3;
1049 uint32 _PAD4:4;
1050 uint32 F:8;
1051 uint32 _PAD5:20;
1052 REG_END
1053
1054 REG128_(GIFPacked, A_D)
1055 uint64 DATA;
1056 uint8 ADDR:8; // enum GIF_A_D_REG
1057 uint8 _PAD1[3+4];
1058 REG_END
1059
1060 REG128_(GIFPacked, NOP)
1061 uint32 _PAD1;
1062 uint32 _PAD2;
1063 uint32 _PAD3;
1064 uint32 _PAD4;
1065 REG_END
1066
1067 REG128_SET(GIFPackedReg)
1068 GIFReg r;
1069 GIFPackedPRIM PRIM;
1070 GIFPackedRGBA RGBA;
1071 GIFPackedSTQ STQ;
1072 GIFPackedUV UV;
1073 GIFPackedXYZF2 XYZF2;
1074 GIFPackedXYZ2 XYZ2;
1075 GIFPackedFOG FOG;
1076 GIFPackedA_D A_D;
1077 GIFPackedNOP NOP;
1078 REG_SET_END
1079
1080 __aligned16 struct GIFPath
1081 {
1082 GIFTag tag;
1083 uint32 reg;
1084 uint32 nreg;
1085 uint32 nloop;
1086 uint32 adonly;
1087 GSVector4i regs;
1088
1089 void SetTag(const void* mem)
1090 {
1091 GSVector4i v = GSVector4i::load<false>(mem);
1092 GSVector4i::store<true>(&tag, v);
1093 reg = 0;
1094 regs = v.uph8(v >> 4) & 0x0f0f0f0f;
1095 nreg = tag.NREG;
1096 nloop = tag.NLOOP;
1097 adonly = nreg == 1 && regs.u8[0] == GIF_REG_A_D;
1098 }
1099
1100 __forceinline uint8 GetReg()
1101 {
1102 return regs.u8[reg]; // GET_GIF_REG(tag, reg);
1103 }
1104
1105 __forceinline bool StepReg()
1106 {
1107 if((++reg & 0xf) == nreg)
1108 {
1109 reg = 0;
1110 if(--nloop == 0)
1111 return false;
1112 }
1113
1114 return true;
1115 }
1116 };
1117
1118 struct GSPrivRegSet
1119 {
1120 union
1121 {
1122 struct
1123 {
1124 GSRegPMODE PMODE;
1125 uint64 _pad1;
1126 GSRegSMODE1 SMODE1;
1127 uint64 _pad2;
1128 GSRegSMODE2 SMODE2;
1129 uint64 _pad3;
1130 GSRegSRFSH SRFSH;
1131 uint64 _pad4;
1132 GSRegSYNCH1 SYNCH1;
1133 uint64 _pad5;
1134 GSRegSYNCH2 SYNCH2;
1135 uint64 _pad6;
1136 GSRegSYNCV SYNCV;
1137 uint64 _pad7;
1138 struct {
1139 GSRegDISPFB DISPFB;
1140 uint64 _pad1;
1141 GSRegDISPLAY DISPLAY;
1142 uint64 _pad2;
1143 } DISP[2];
1144 GSRegEXTBUF EXTBUF;
1145 uint64 _pad8;
1146 GSRegEXTDATA EXTDATA;
1147 uint64 _pad9;
1148 GSRegEXTWRITE EXTWRITE;
1149 uint64 _pad10;
1150 GSRegBGCOLOR BGCOLOR;
1151 uint64 _pad11;
1152 };
1153
1154 uint8 _pad12[0x1000];
1155 };
1156
1157 union
1158 {
1159 struct
1160 {
1161 GSRegCSR CSR;
1162 uint64 _pad13;
1163 GSRegIMR IMR;
1164 uint64 _pad14;
1165 uint64 _unk1[4];
1166 GSRegBUSDIR BUSDIR;
1167 uint64 _pad15;
1168 uint64 _unk2[6];
1169 GSRegSIGLBLID SIGLBLID;
1170 uint64 _pad16;
1171 };
1172
1173 uint8 _pad17[0x1000];
1174 };
1175 };
1176
1177 #pragma pack(pop)
1178
1179 enum {KEYPRESS=1, KEYRELEASE=2};
1180 struct GSKeyEventData {uint32 key, type;};
1181
1182 enum {FREEZE_LOAD=0, FREEZE_SAVE=1, FREEZE_SIZE=2};
1183 struct GSFreezeData {int size; uint8* data;};
1184
1185 enum stateType {ST_WRITE, ST_TRANSFER, ST_VSYNC};

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