/[pcsx2_0.9.7]/trunk/plugins/GSdx/GS.h
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Contents of /trunk/plugins/GSdx/GS.h

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Revision 62 - (show annotations) (download)
Tue Sep 7 11:08:22 2010 UTC (9 years, 9 months ago) by william
File MIME type: text/plain
File size: 20470 byte(s)
Auto Commited Import of: pcsx2-0.9.7-r3738-debug in ./trunk
1 /*
2 * Copyright (C) 2007-2009 Gabest
3 * http://www.gabest.org
4 *
5 * This Program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2, or (at your option)
8 * any later version.
9 *
10 * This Program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with GNU Make; see the file COPYING. If not, write to
17 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
18 * http://www.gnu.org/copyleft/gpl.html
19 *
20 * Special Notes:
21 *
22 * Register definitions and most of the enums originate from sps2dev-0.4.0
23 * Copyright (C) 2002 Terratron Technologies Inc. All Rights Reserved.
24 *
25 */
26
27 #pragma once
28
29 #define PLUGIN_VERSION 16
30
31 #define MAX_PAGES 512
32 #define MAX_BLOCKS 16384
33
34 #include "GSVector.h"
35
36 #pragma pack(push, 1)
37
38 //
39 // sps2registers.h
40 //
41
42 enum GS_PRIM
43 {
44 GS_POINTLIST = 0,
45 GS_LINELIST = 1,
46 GS_LINESTRIP = 2,
47 GS_TRIANGLELIST = 3,
48 GS_TRIANGLESTRIP = 4,
49 GS_TRIANGLEFAN = 5,
50 GS_SPRITE = 6,
51 GS_INVALID = 7,
52 };
53
54 enum GS_PRIM_CLASS
55 {
56 GS_POINT_CLASS = 0,
57 GS_LINE_CLASS = 1,
58 GS_TRIANGLE_CLASS = 2,
59 GS_SPRITE_CLASS = 3,
60 GS_INVALID_CLASS = 7,
61 };
62
63 enum GIF_REG
64 {
65 GIF_REG_PRIM = 0x00,
66 GIF_REG_RGBA = 0x01,
67 GIF_REG_STQ = 0x02,
68 GIF_REG_UV = 0x03,
69 GIF_REG_XYZF2 = 0x04,
70 GIF_REG_XYZ2 = 0x05,
71 GIF_REG_TEX0_1 = 0x06,
72 GIF_REG_TEX0_2 = 0x07,
73 GIF_REG_CLAMP_1 = 0x08,
74 GIF_REG_CLAMP_2 = 0x09,
75 GIF_REG_FOG = 0x0a,
76 GIF_REG_XYZF3 = 0x0c,
77 GIF_REG_XYZ3 = 0x0d,
78 GIF_REG_A_D = 0x0e,
79 GIF_REG_NOP = 0x0f,
80 };
81
82 enum GIF_A_D_REG
83 {
84 GIF_A_D_REG_PRIM = 0x00,
85 GIF_A_D_REG_RGBAQ = 0x01,
86 GIF_A_D_REG_ST = 0x02,
87 GIF_A_D_REG_UV = 0x03,
88 GIF_A_D_REG_XYZF2 = 0x04,
89 GIF_A_D_REG_XYZ2 = 0x05,
90 GIF_A_D_REG_TEX0_1 = 0x06,
91 GIF_A_D_REG_TEX0_2 = 0x07,
92 GIF_A_D_REG_CLAMP_1 = 0x08,
93 GIF_A_D_REG_CLAMP_2 = 0x09,
94 GIF_A_D_REG_FOG = 0x0a,
95 GIF_A_D_REG_XYZF3 = 0x0c,
96 GIF_A_D_REG_XYZ3 = 0x0d,
97 GIF_A_D_REG_NOP = 0x0f,
98 GIF_A_D_REG_TEX1_1 = 0x14,
99 GIF_A_D_REG_TEX1_2 = 0x15,
100 GIF_A_D_REG_TEX2_1 = 0x16,
101 GIF_A_D_REG_TEX2_2 = 0x17,
102 GIF_A_D_REG_XYOFFSET_1 = 0x18,
103 GIF_A_D_REG_XYOFFSET_2 = 0x19,
104 GIF_A_D_REG_PRMODECONT = 0x1a,
105 GIF_A_D_REG_PRMODE = 0x1b,
106 GIF_A_D_REG_TEXCLUT = 0x1c,
107 GIF_A_D_REG_SCANMSK = 0x22,
108 GIF_A_D_REG_MIPTBP1_1 = 0x34,
109 GIF_A_D_REG_MIPTBP1_2 = 0x35,
110 GIF_A_D_REG_MIPTBP2_1 = 0x36,
111 GIF_A_D_REG_MIPTBP2_2 = 0x37,
112 GIF_A_D_REG_TEXA = 0x3b,
113 GIF_A_D_REG_FOGCOL = 0x3d,
114 GIF_A_D_REG_TEXFLUSH = 0x3f,
115 GIF_A_D_REG_SCISSOR_1 = 0x40,
116 GIF_A_D_REG_SCISSOR_2 = 0x41,
117 GIF_A_D_REG_ALPHA_1 = 0x42,
118 GIF_A_D_REG_ALPHA_2 = 0x43,
119 GIF_A_D_REG_DIMX = 0x44,
120 GIF_A_D_REG_DTHE = 0x45,
121 GIF_A_D_REG_COLCLAMP = 0x46,
122 GIF_A_D_REG_TEST_1 = 0x47,
123 GIF_A_D_REG_TEST_2 = 0x48,
124 GIF_A_D_REG_PABE = 0x49,
125 GIF_A_D_REG_FBA_1 = 0x4a,
126 GIF_A_D_REG_FBA_2 = 0x4b,
127 GIF_A_D_REG_FRAME_1 = 0x4c,
128 GIF_A_D_REG_FRAME_2 = 0x4d,
129 GIF_A_D_REG_ZBUF_1 = 0x4e,
130 GIF_A_D_REG_ZBUF_2 = 0x4f,
131 GIF_A_D_REG_BITBLTBUF = 0x50,
132 GIF_A_D_REG_TRXPOS = 0x51,
133 GIF_A_D_REG_TRXREG = 0x52,
134 GIF_A_D_REG_TRXDIR = 0x53,
135 GIF_A_D_REG_HWREG = 0x54,
136 GIF_A_D_REG_SIGNAL = 0x60,
137 GIF_A_D_REG_FINISH = 0x61,
138 GIF_A_D_REG_LABEL = 0x62,
139 };
140
141 enum GIF_FLG
142 {
143 GIF_FLG_PACKED = 0,
144 GIF_FLG_REGLIST = 1,
145 GIF_FLG_IMAGE = 2,
146 GIF_FLG_IMAGE2 = 3
147 };
148
149 enum GS_PSM
150 {
151 PSM_PSMCT32 = 0, // 0000-0000
152 PSM_PSMCT24 = 1, // 0000-0001
153 PSM_PSMCT16 = 2, // 0000-0010
154 PSM_PSMCT16S = 10, // 0000-1010
155 PSM_PSMT8 = 19, // 0001-0011
156 PSM_PSMT4 = 20, // 0001-0100
157 PSM_PSMT8H = 27, // 0001-1011
158 PSM_PSMT4HL = 36, // 0010-0100
159 PSM_PSMT4HH = 44, // 0010-1100
160 PSM_PSMZ32 = 48, // 0011-0000
161 PSM_PSMZ24 = 49, // 0011-0001
162 PSM_PSMZ16 = 50, // 0011-0010
163 PSM_PSMZ16S = 58, // 0011-1010
164 };
165
166 enum GS_TFX
167 {
168 TFX_MODULATE = 0,
169 TFX_DECAL = 1,
170 TFX_HIGHLIGHT = 2,
171 TFX_HIGHLIGHT2 = 3,
172 TFX_NONE = 4,
173 };
174
175 enum GS_CLAMP
176 {
177 CLAMP_REPEAT = 0,
178 CLAMP_CLAMP = 1,
179 CLAMP_REGION_CLAMP = 2,
180 CLAMP_REGION_REPEAT = 3,
181 };
182
183 enum GS_ZTST
184 {
185 ZTST_NEVER = 0,
186 ZTST_ALWAYS = 1,
187 ZTST_GEQUAL = 2,
188 ZTST_GREATER = 3,
189 };
190
191 enum GS_ATST
192 {
193 ATST_NEVER = 0,
194 ATST_ALWAYS = 1,
195 ATST_LESS = 2,
196 ATST_LEQUAL = 3,
197 ATST_EQUAL = 4,
198 ATST_GEQUAL = 5,
199 ATST_GREATER = 6,
200 ATST_NOTEQUAL = 7,
201 };
202
203 enum GS_AFAIL
204 {
205 AFAIL_KEEP = 0,
206 AFAIL_FB_ONLY = 1,
207 AFAIL_ZB_ONLY = 2,
208 AFAIL_RGB_ONLY = 3,
209 };
210
211 //
212 // sps2regstructs.h
213 //
214
215 #define REG32(name) \
216 union name \
217 { \
218 uint32 u32; \
219 struct { \
220
221 #define REG64(name) \
222 union name \
223 { \
224 uint64 u64; \
225 uint32 u32[2]; \
226 void operator = (const GSVector4i& v) {GSVector4i::storel(this, v);} \
227 bool operator == (const union name& r) const {return ((GSVector4i)r).eq(*this);} \
228 bool operator != (const union name& r) const {return !((GSVector4i)r).eq(*this);} \
229 operator GSVector4i() const {return GSVector4i::loadl(this);} \
230 struct { \
231
232 #define REG128(name)\
233 union name \
234 { \
235 uint64 u64[2]; \
236 uint32 u32[4]; \
237 struct { \
238
239 #define REG32_(prefix, name) REG32(prefix##name)
240 #define REG64_(prefix, name) REG64(prefix##name)
241 #define REG128_(prefix, name) REG128(prefix##name)
242
243 #define REG_END }; };
244 #define REG_END2 };
245
246 #define REG32_SET(name) \
247 union name \
248 { \
249 uint32 u32; \
250
251 #define REG64_SET(name) \
252 union name \
253 { \
254 uint64 u64; \
255 uint32 u32[2]; \
256
257 #define REG128_SET(name)\
258 union name \
259 { \
260 __m128i m128; \
261 uint64 u64[2]; \
262 uint32 u32[4]; \
263
264 #define REG_SET_END };
265
266 REG64_(GSReg, BGCOLOR)
267 uint8 R;
268 uint8 G;
269 uint8 B;
270 uint8 _PAD1[5];
271 REG_END
272
273 REG64_(GSReg, BUSDIR)
274 uint32 DIR:1;
275 uint32 _PAD1:31;
276 uint32 _PAD2:32;
277 REG_END
278
279 REG64_(GSReg, CSR)
280 uint32 rSIGNAL:1;
281 uint32 rFINISH:1;
282 uint32 rHSINT:1;
283 uint32 rVSINT:1;
284 uint32 rEDWINT:1;
285 uint32 rZERO1:1;
286 uint32 rZERO2:1;
287 uint32 r_PAD1:1;
288 uint32 rFLUSH:1;
289 uint32 rRESET:1;
290 uint32 r_PAD2:2;
291 uint32 rNFIELD:1;
292 uint32 rFIELD:1;
293 uint32 rFIFO:2;
294 uint32 rREV:8;
295 uint32 rID:8;
296 uint32 wSIGNAL:1;
297 uint32 wFINISH:1;
298 uint32 wHSINT:1;
299 uint32 wVSINT:1;
300 uint32 wEDWINT:1;
301 uint32 wZERO1:1;
302 uint32 wZERO2:1;
303 uint32 w_PAD1:1;
304 uint32 wFLUSH:1;
305 uint32 wRESET:1;
306 uint32 w_PAD2:2;
307 uint32 wNFIELD:1;
308 uint32 wFIELD:1;
309 uint32 wFIFO:2;
310 uint32 wREV:8;
311 uint32 wID:8;
312 REG_END
313
314 REG64_(GSReg, DISPFB) // (-1/2)
315 uint32 FBP:9;
316 uint32 FBW:6;
317 uint32 PSM:5;
318 uint32 _PAD:12;
319 uint32 DBX:11;
320 uint32 DBY:11;
321 uint32 _PAD2:10;
322 REG_END2
323 uint32 Block() const {return FBP << 5;}
324 REG_END2
325
326 REG64_(GSReg, DISPLAY) // (-1/2)
327 uint32 DX:12;
328 uint32 DY:11;
329 uint32 MAGH:4;
330 uint32 MAGV:2;
331 uint32 _PAD:3;
332 uint32 DW:12;
333 uint32 DH:11;
334 uint32 _PAD2:9;
335 REG_END
336
337 REG64_(GSReg, EXTBUF)
338 uint32 EXBP:14;
339 uint32 EXBW:6;
340 uint32 FBIN:2;
341 uint32 WFFMD:1;
342 uint32 EMODA:2;
343 uint32 EMODC:2;
344 uint32 _PAD1:5;
345 uint32 WDX:11;
346 uint32 WDY:11;
347 uint32 _PAD2:10;
348 REG_END
349
350 REG64_(GSReg, EXTDATA)
351 uint32 SX:12;
352 uint32 SY:11;
353 uint32 SMPH:4;
354 uint32 SMPV:2;
355 uint32 _PAD1:3;
356 uint32 WW:12;
357 uint32 WH:11;
358 uint32 _PAD2:9;
359 REG_END
360
361 REG64_(GSReg, EXTWRITE)
362 uint32 WRITE:1;
363 uint32 _PAD1:31;
364 uint32 _PAD2:32;
365 REG_END
366
367 REG64_(GSReg, IMR)
368 uint32 _PAD1:8;
369 uint32 SIGMSK:1;
370 uint32 FINISHMSK:1;
371 uint32 HSMSK:1;
372 uint32 VSMSK:1;
373 uint32 EDWMSK:1;
374 uint32 _PAD2:19;
375 uint32 _PAD3:32;
376 REG_END
377
378 REG64_(GSReg, PMODE)
379 union
380 {
381 struct
382 {
383 uint32 EN1:1;
384 uint32 EN2:1;
385 uint32 CRTMD:3;
386 uint32 MMOD:1;
387 uint32 AMOD:1;
388 uint32 SLBG:1;
389 uint32 ALP:8;
390 uint32 _PAD:16;
391 uint32 _PAD1:32;
392 };
393
394 struct
395 {
396 uint32 EN:2;
397 uint32 _PAD2:30;
398 uint32 _PAD3:32;
399 };
400 };
401 REG_END
402
403 REG64_(GSReg, SIGLBLID)
404 uint32 SIGID;
405 uint32 LBLID;
406 REG_END
407
408 REG64_(GSReg, SMODE1)
409 uint32 RC:3;
410 uint32 LC:7;
411 uint32 T1248:2;
412 uint32 SLCK:1;
413 uint32 CMOD:2;
414 uint32 EX:1;
415 uint32 PRST:1;
416 uint32 SINT:1;
417 uint32 XPCK:1;
418 uint32 PCK2:2;
419 uint32 SPML:4;
420 uint32 GCONT:1; // YCrCb
421 uint32 PHS:1;
422 uint32 PVS:1;
423 uint32 PEHS:1;
424 uint32 PEVS:1;
425 uint32 CLKSEL:2;
426 uint32 NVCK:1;
427 uint32 SLCK2:1;
428 uint32 VCKSEL:2;
429 uint32 VHP:1;
430 uint32 _PAD1:27;
431 REG_END
432
433 /*
434
435 // pal
436
437 CLKSEL=1 CMOD=3 EX=0 GCONT=0 LC=32 NVCK=1 PCK2=0 PEHS=0 PEVS=0 PHS=0 PRST=1 PVS=0 RC=4 SINT=0 SLCK=0 SLCK2=1 SPML=4 T1248=1 VCKSEL=1 VHP=0 XPCK=0
438
439 // ntsc
440
441 CLKSEL=1 CMOD=2 EX=0 GCONT=0 LC=32 NVCK=1 PCK2=0 PEHS=0 PEVS=0 PHS=0 PRST=1 PVS=0 RC=4 SINT=0 SLCK=0 SLCK2=1 SPML=4 T1248=1 VCKSEL=1 VHP=0 XPCK=0
442
443 // ntsc progressive (SoTC)
444
445 CLKSEL=1 CMOD=0 EX=0 GCONT=0 LC=32 NVCK=1 PCK2=0 PEHS=0 PEVS=0 PHS=0 PRST=1 PVS=0 RC=4 SINT=0 SLCK=0 SLCK2=1 SPML=2 T1248=1 VCKSEL=1 VHP=1 XPCK=0
446
447 */
448
449 REG64_(GSReg, SMODE2)
450 uint32 INT:1;
451 uint32 FFMD:1;
452 uint32 DPMS:2;
453 uint32 _PAD2:28;
454 uint32 _PAD3:32;
455 REG_END
456
457 REG64_(GSReg, SRFSH)
458 uint32 _DUMMY;
459 // TODO
460 REG_END
461
462 REG64_(GSReg, SYNCH1)
463 uint32 _DUMMY;
464 // TODO
465 REG_END
466
467 REG64_(GSReg, SYNCH2)
468 uint32 _DUMMY;
469 // TODO
470 REG_END
471
472 REG64_(GSReg, SYNCV)
473 uint64 _DUMMY;
474 // TODO
475 REG_END
476
477 REG64_SET(GSReg)
478 GSRegBGCOLOR BGCOLOR;
479 GSRegBUSDIR BUSDIR;
480 GSRegCSR CSR;
481 GSRegDISPFB DISPFB;
482 GSRegDISPLAY DISPLAY;
483 GSRegEXTBUF EXTBUF;
484 GSRegEXTDATA EXTDATA;
485 GSRegEXTWRITE EXTWRITE;
486 GSRegIMR IMR;
487 GSRegPMODE PMODE;
488 GSRegSIGLBLID SIGLBLID;
489 GSRegSMODE1 SMODE1;
490 GSRegSMODE2 SMODE2;
491 REG_SET_END
492
493 //
494 // sps2tags.h
495 //
496
497 #define SET_GIF_REG(gifTag, iRegNo, uiValue) \
498 {((GIFTag*)&gifTag)->u64[1] |= (((uiValue) & 0xf) << ((iRegNo) << 2));}
499
500 #ifdef _M_AMD64
501 #define GET_GIF_REG(tag, reg) \
502 (((tag).u64[1] >> ((reg) << 2)) & 0xf)
503 #else
504 #define GET_GIF_REG(tag, reg) \
505 (((tag).u32[2 + ((reg) >> 3)] >> (((reg) & 7) << 2)) & 0xf)
506 #endif
507
508 //
509 // GIFTag
510
511 REG128(GIFTag)
512 uint32 NLOOP:15;
513 uint32 EOP:1;
514 uint32 _PAD1:16;
515 uint32 _PAD2:14;
516 uint32 PRE:1;
517 uint32 PRIM:11;
518 uint32 FLG:2; // enum GIF_FLG
519 uint32 NREG:4;
520 uint64 REGS;
521 REG_END
522
523 // GIFReg
524
525 REG64_(GIFReg, ALPHA)
526 uint32 A:2;
527 uint32 B:2;
528 uint32 C:2;
529 uint32 D:2;
530 uint32 _PAD1:24;
531 uint8 FIX;
532 uint8 _PAD2[3];
533 REG_END2
534 // opaque => output will be Cs/As
535 __forceinline bool IsOpaque() const {return (A == B || C == 2 && FIX == 0) && D == 0 || (A == 0 && B == D && C == 2 && FIX == 0x80);}
536 __forceinline bool IsOpaque(int amin, int amax) const {return (A == B || amax == 0) && D == 0 || A == 0 && B == D && amin == 0x80 && amax == 0x80;}
537 REG_END2
538
539 REG64_(GIFReg, BITBLTBUF)
540 uint32 SBP:14;
541 uint32 _PAD1:2;
542 uint32 SBW:6;
543 uint32 _PAD2:2;
544 uint32 SPSM:6;
545 uint32 _PAD3:2;
546 uint32 DBP:14;
547 uint32 _PAD4:2;
548 uint32 DBW:6;
549 uint32 _PAD5:2;
550 uint32 DPSM:6;
551 uint32 _PAD6:2;
552 REG_END
553
554 REG64_(GIFReg, CLAMP)
555 union
556 {
557 struct
558 {
559 uint32 WMS:2;
560 uint32 WMT:2;
561 uint32 MINU:10;
562 uint32 MAXU:10;
563 uint32 _PAD1:8;
564 uint32 _PAD2:2;
565 uint32 MAXV:10;
566 uint32 _PAD3:20;
567 };
568
569 struct
570 {
571 uint64 _PAD4:24;
572 uint64 MINV:10;
573 uint64 _PAD5:30;
574 };
575 };
576 REG_END
577
578 REG64_(GIFReg, COLCLAMP)
579 uint32 CLAMP:1;
580 uint32 _PAD1:31;
581 uint32 _PAD2:32;
582 REG_END
583
584 REG64_(GIFReg, DIMX)
585 int32 DM00:3;
586 int32 _PAD00:1;
587 int32 DM01:3;
588 int32 _PAD01:1;
589 int32 DM02:3;
590 int32 _PAD02:1;
591 int32 DM03:3;
592 int32 _PAD03:1;
593 int32 DM10:3;
594 int32 _PAD10:1;
595 int32 DM11:3;
596 int32 _PAD11:1;
597 int32 DM12:3;
598 int32 _PAD12:1;
599 int32 DM13:3;
600 int32 _PAD13:1;
601 int32 DM20:3;
602 int32 _PAD20:1;
603 int32 DM21:3;
604 int32 _PAD21:1;
605 int32 DM22:3;
606 int32 _PAD22:1;
607 int32 DM23:3;
608 int32 _PAD23:1;
609 int32 DM30:3;
610 int32 _PAD30:1;
611 int32 DM31:3;
612 int32 _PAD31:1;
613 int32 DM32:3;
614 int32 _PAD32:1;
615 int32 DM33:3;
616 int32 _PAD33:1;
617 REG_END
618
619 REG64_(GIFReg, DTHE)
620 uint32 DTHE:1;
621 uint32 _PAD1:31;
622 uint32 _PAD2:32;
623 REG_END
624
625 REG64_(GIFReg, FBA)
626 uint32 FBA:1;
627 uint32 _PAD1:31;
628 uint32 _PAD2:32;
629 REG_END
630
631 REG64_(GIFReg, FINISH)
632 uint32 _PAD1[2];
633 REG_END
634
635 REG64_(GIFReg, FOG)
636 uint8 _PAD1[4+3];
637 uint8 F:8;
638 REG_END
639
640 REG64_(GIFReg, FOGCOL)
641 uint8 FCR;
642 uint8 FCG;
643 uint8 FCB;
644 uint8 _PAD1[5];
645 REG_END
646
647 REG64_(GIFReg, FRAME)
648 uint32 FBP:9;
649 uint32 _PAD1:7;
650 uint32 FBW:6;
651 uint32 _PAD2:2;
652 uint32 PSM:6;
653 uint32 _PAD3:2;
654 uint32 FBMSK;
655 REG_END2
656 uint32 Block() const {return FBP << 5;}
657 REG_END2
658
659 REG64_(GIFReg, HWREG)
660 uint32 DATA_LOWER;
661 uint32 DATA_UPPER;
662 REG_END
663
664 REG64_(GIFReg, LABEL)
665 uint32 ID;
666 uint32 IDMSK;
667 REG_END
668
669 REG64_(GIFReg, MIPTBP1)
670 uint64 TBP1:14;
671 uint64 TBW1:6;
672 uint64 TBP2:14;
673 uint64 TBW2:6;
674 uint64 TBP3:14;
675 uint64 TBW3:6;
676 uint64 _PAD:4;
677 REG_END
678
679 REG64_(GIFReg, MIPTBP2)
680 uint64 TBP4:14;
681 uint64 TBW4:6;
682 uint64 TBP5:14;
683 uint64 TBW5:6;
684 uint64 TBP6:14;
685 uint64 TBW6:6;
686 uint64 _PAD:4;
687 REG_END
688
689 REG64_(GIFReg, NOP)
690 uint32 _PAD[2];
691 REG_END
692
693 REG64_(GIFReg, PABE)
694 uint32 PABE:1;
695 uint32 _PAD1:31;
696 uint32 _PAD2:32;
697 REG_END
698
699 REG64_(GIFReg, PRIM)
700 uint32 PRIM:3;
701 uint32 IIP:1;
702 uint32 TME:1;
703 uint32 FGE:1;
704 uint32 ABE:1;
705 uint32 AA1:1;
706 uint32 FST:1;
707 uint32 CTXT:1;
708 uint32 FIX:1;
709 uint32 _PAD1:21;
710 uint32 _PAD2:32;
711 REG_END
712
713 REG64_(GIFReg, PRMODE)
714 uint32 _PRIM:3;
715 uint32 IIP:1;
716 uint32 TME:1;
717 uint32 FGE:1;
718 uint32 ABE:1;
719 uint32 AA1:1;
720 uint32 FST:1;
721 uint32 CTXT:1;
722 uint32 FIX:1;
723 uint32 _PAD2:21;
724 uint32 _PAD3:32;
725 REG_END
726
727 REG64_(GIFReg, PRMODECONT)
728 uint32 AC:1;
729 uint32 _PAD1:31;
730 uint32 _PAD2:32;
731 REG_END
732
733 REG64_(GIFReg, RGBAQ)
734 uint8 R;
735 uint8 G;
736 uint8 B;
737 uint8 A;
738 float Q;
739 REG_END
740
741 REG64_(GIFReg, SCANMSK)
742 uint32 MSK:2;
743 uint32 _PAD1:30;
744 uint32 _PAD2:32;
745 REG_END
746
747 REG64_(GIFReg, SCISSOR)
748 uint32 SCAX0:11;
749 uint32 _PAD1:5;
750 uint32 SCAX1:11;
751 uint32 _PAD2:5;
752 uint32 SCAY0:11;
753 uint32 _PAD3:5;
754 uint32 SCAY1:11;
755 uint32 _PAD4:5;
756 REG_END
757
758 REG64_(GIFReg, SIGNAL)
759 uint32 ID;
760 uint32 IDMSK;
761 REG_END
762
763 REG64_(GIFReg, ST)
764 float S;
765 float T;
766 REG_END
767
768 REG64_(GIFReg, TEST)
769 uint32 ATE:1;
770 uint32 ATST:3;
771 uint32 AREF:8;
772 uint32 AFAIL:2;
773 uint32 DATE:1;
774 uint32 DATM:1;
775 uint32 ZTE:1;
776 uint32 ZTST:2;
777 uint32 _PAD1:13;
778 uint32 _PAD2:32;
779 REG_END2
780 __forceinline bool DoFirstPass() {return !ATE || ATST != ATST_NEVER;} // not all pixels fail automatically
781 __forceinline bool DoSecondPass() {return ATE && ATST != ATST_ALWAYS && AFAIL != AFAIL_KEEP;} // pixels may fail, write fb/z
782 __forceinline bool NoSecondPass() {return ATE && ATST != ATST_ALWAYS && AFAIL == AFAIL_KEEP;} // pixels may fail, no output
783 REG_END2
784
785 REG64_(GIFReg, TEX0)
786 union
787 {
788 struct
789 {
790 uint32 TBP0:14;
791 uint32 TBW:6;
792 uint32 PSM:6;
793 uint32 TW:4;
794 uint32 _PAD1:2;
795 uint32 _PAD2:2;
796 uint32 TCC:1;
797 uint32 TFX:2;
798 uint32 CBP:14;
799 uint32 CPSM:4;
800 uint32 CSM:1;
801 uint32 CSA:5;
802 uint32 CLD:3;
803 };
804
805 struct
806 {
807 uint64 _PAD3:30;
808 uint64 TH:4;
809 uint64 _PAD4:30;
810 };
811 };
812 REG_END2
813 __forceinline bool IsRepeating() {return ((uint32)1 << TW) > (TBW << 6);}
814 REG_END2
815
816 REG64_(GIFReg, TEX1)
817 uint32 LCM:1;
818 uint32 _PAD1:1;
819 uint32 MXL:3;
820 uint32 MMAG:1;
821 uint32 MMIN:3;
822 uint32 MTBA:1;
823 uint32 _PAD2:9;
824 uint32 L:2;
825 uint32 _PAD3:11;
826 int32 K:12; // 1:7:4
827 uint32 _PAD4:20;
828 REG_END2
829 bool IsMinLinear() const {return (MMIN == 1) || (MMIN & 4);}
830 bool IsMagLinear() const {return MMAG;}
831 REG_END2
832
833 REG64_(GIFReg, TEX2)
834 uint32 _PAD1:20;
835 uint32 PSM:6;
836 uint32 _PAD2:6;
837 uint32 _PAD3:5;
838 uint32 CBP:14;
839 uint32 CPSM:4;
840 uint32 CSM:1;
841 uint32 CSA:5;
842 uint32 CLD:3;
843 REG_END
844
845 REG64_(GIFReg, TEXA)
846 uint8 TA0;
847 uint8 _PAD1:7;
848 uint8 AEM:1;
849 uint16 _PAD2;
850 uint8 TA1:8;
851 uint8 _PAD3[3];
852 REG_END
853
854 REG64_(GIFReg, TEXCLUT)
855 uint32 CBW:6;
856 uint32 COU:6;
857 uint32 COV:10;
858 uint32 _PAD1:10;
859 uint32 _PAD2:32;
860 REG_END
861
862 REG64_(GIFReg, TEXFLUSH)
863 uint32 _PAD1:32;
864 uint32 _PAD2:32;
865 REG_END
866
867 REG64_(GIFReg, TRXDIR)
868 uint32 XDIR:2;
869 uint32 _PAD1:30;
870 uint32 _PAD2:32;
871 REG_END
872
873 REG64_(GIFReg, TRXPOS)
874 uint32 SSAX:11;
875 uint32 _PAD1:5;
876 uint32 SSAY:11;
877 uint32 _PAD2:5;
878 uint32 DSAX:11;
879 uint32 _PAD3:5;
880 uint32 DSAY:11;
881 uint32 DIRY:1;
882 uint32 DIRX:1;
883 uint32 _PAD4:3;
884 REG_END
885
886 REG64_(GIFReg, TRXREG)
887 uint32 RRW:12;
888 uint32 _PAD1:20;
889 uint32 RRH:12;
890 uint32 _PAD2:20;
891 REG_END
892
893 // GSState::GIFPackedRegHandlerUV and GSState::GIFRegHandlerUV will make sure that the _PAD1/2 bits are set to zero
894
895 REG64_(GIFReg, UV)
896 uint16 U;
897 // uint32 _PAD1:2;
898 uint16 V;
899 // uint32 _PAD2:2;
900 uint32 _PAD3;
901 REG_END
902
903 // GSState::GIFRegHandlerXYOFFSET will make sure that the _PAD1/2 bits are set to zero
904
905 REG64_(GIFReg, XYOFFSET)
906 uint32 OFX; // :16; uint32 _PAD1:16;
907 uint32 OFY; // :16; uint32 _PAD2:16;
908 REG_END
909
910 REG64_(GIFReg, XYZ)
911 uint16 X;
912 uint16 Y;
913 uint32 Z;
914 REG_END
915
916 REG64_(GIFReg, XYZF)
917 uint16 X;
918 uint16 Y;
919 uint32 Z:24;
920 uint32 F:8;
921 REG_END
922
923 REG64_(GIFReg, ZBUF)
924 uint32 ZBP:9;
925 uint32 _PAD1:15;
926 // uint32 PSM:4;
927 // uint32 _PAD2:4;
928 uint32 PSM:6;
929 uint32 _PAD2:2;
930 uint32 ZMSK:1;
931 uint32 _PAD3:31;
932 REG_END2
933 uint32 Block() const {return ZBP << 5;}
934 REG_END2
935
936 REG64_SET(GIFReg)
937 GIFRegALPHA ALPHA;
938 GIFRegBITBLTBUF BITBLTBUF;
939 GIFRegCLAMP CLAMP;
940 GIFRegCOLCLAMP COLCLAMP;
941 GIFRegDIMX DIMX;
942 GIFRegDTHE DTHE;
943 GIFRegFBA FBA;
944 GIFRegFINISH FINISH;
945 GIFRegFOG FOG;
946 GIFRegFOGCOL FOGCOL;
947 GIFRegFRAME FRAME;
948 GIFRegHWREG HWREG;
949 GIFRegLABEL LABEL;
950 GIFRegMIPTBP1 MIPTBP1;
951 GIFRegMIPTBP2 MIPTBP2;
952 GIFRegNOP NOP;
953 GIFRegPABE PABE;
954 GIFRegPRIM PRIM;
955 GIFRegPRMODE PRMODE;
956 GIFRegPRMODECONT PRMODECONT;
957 GIFRegRGBAQ RGBAQ;
958 GIFRegSCANMSK SCANMSK;
959 GIFRegSCISSOR SCISSOR;
960 GIFRegSIGNAL SIGNAL;
961 GIFRegST ST;
962 GIFRegTEST TEST;
963 GIFRegTEX0 TEX0;
964 GIFRegTEX1 TEX1;
965 GIFRegTEX2 TEX2;
966 GIFRegTEXA TEXA;
967 GIFRegTEXCLUT TEXCLUT;
968 GIFRegTEXFLUSH TEXFLUSH;
969 GIFRegTRXDIR TRXDIR;
970 GIFRegTRXPOS TRXPOS;
971 GIFRegTRXREG TRXREG;
972 GIFRegUV UV;
973 GIFRegXYOFFSET XYOFFSET;
974 GIFRegXYZ XYZ;
975 GIFRegXYZF XYZF;
976 GIFRegZBUF ZBUF;
977 REG_SET_END
978
979 // GIFPacked
980
981 REG128_(GIFPacked, PRIM)
982 uint32 PRIM:11;
983 uint32 _PAD1:21;
984 uint32 _PAD2[3];
985 REG_END
986
987 REG128_(GIFPacked, RGBA)
988 uint8 R;
989 uint8 _PAD1[3];
990 uint8 G;
991 uint8 _PAD2[3];
992 uint8 B;
993 uint8 _PAD3[3];
994 uint8 A;
995 uint8 _PAD4[3];
996 REG_END
997
998 REG128_(GIFPacked, STQ)
999 float S;
1000 float T;
1001 float Q;
1002 uint32 _PAD1:32;
1003 REG_END
1004
1005 REG128_(GIFPacked, UV)
1006 uint32 U:14;
1007 uint32 _PAD1:18;
1008 uint32 V:14;
1009 uint32 _PAD2:18;
1010 uint32 _PAD3:32;
1011 uint32 _PAD4:32;
1012 REG_END
1013
1014 REG128_(GIFPacked, XYZF2)
1015 uint16 X;
1016 uint16 _PAD1;
1017 uint16 Y;
1018 uint16 _PAD2;
1019
1020 uint32 _PAD3:4;
1021 uint32 Z:24;
1022 uint32 _PAD4:4;
1023 uint32 _PAD5:4;
1024 uint32 F:8;
1025 uint32 _PAD6:3;
1026 uint32 ADC:1;
1027 uint32 _PAD7:16;
1028 REG_END
1029
1030 REG128_(GIFPacked, XYZ2)
1031 uint16 X;
1032 uint16 _PAD1;
1033 uint16 Y;
1034 uint16 _PAD2;
1035 uint32 Z;
1036 uint32 _PAD3:15;
1037 uint32 ADC:1;
1038 uint32 _PAD4:16;
1039 REG_END
1040
1041 REG128_(GIFPacked, FOG)
1042 uint32 _PAD1;
1043 uint32 _PAD2;
1044 uint32 _PAD3;
1045 uint32 _PAD4:4;
1046 uint32 F:8;
1047 uint32 _PAD5:20;
1048 REG_END
1049
1050 REG128_(GIFPacked, A_D)
1051 uint64 DATA;
1052 uint8 ADDR:8; // enum GIF_A_D_REG
1053 uint8 _PAD1[3+4];
1054 REG_END
1055
1056 REG128_(GIFPacked, NOP)
1057 uint32 _PAD1;
1058 uint32 _PAD2;
1059 uint32 _PAD3;
1060 uint32 _PAD4;
1061 REG_END
1062
1063 REG128_SET(GIFPackedReg)
1064 GIFReg r;
1065 GIFPackedPRIM PRIM;
1066 GIFPackedRGBA RGBA;
1067 GIFPackedSTQ STQ;
1068 GIFPackedUV UV;
1069 GIFPackedXYZF2 XYZF2;
1070 GIFPackedXYZ2 XYZ2;
1071 GIFPackedFOG FOG;
1072 GIFPackedA_D A_D;
1073 GIFPackedNOP NOP;
1074 REG_SET_END
1075
1076 __aligned16 struct GIFPath
1077 {
1078 GIFTag tag;
1079 uint32 reg;
1080 uint32 nreg;
1081 uint32 nloop;
1082 uint32 adonly;
1083 GSVector4i regs;
1084
1085 void SetTag(const void* mem)
1086 {
1087 GSVector4i v = GSVector4i::load<false>(mem);
1088 GSVector4i::store<true>(&tag, v);
1089 reg = 0;
1090 regs = v.uph8(v >> 4) & 0x0f0f0f0f;
1091 nreg = tag.NREG;
1092 nloop = tag.NLOOP;
1093 adonly = nreg == 1 && regs.u8[0] == GIF_REG_A_D;
1094 }
1095
1096 __forceinline uint8 GetReg()
1097 {
1098 return regs.u8[reg]; // GET_GIF_REG(tag, reg);
1099 }
1100
1101 __forceinline bool StepReg()
1102 {
1103 if((++reg & 0xf) == nreg)
1104 {
1105 reg = 0;
1106 if(--nloop == 0)
1107 return false;
1108 }
1109
1110 return true;
1111 }
1112 };
1113
1114 struct GSPrivRegSet
1115 {
1116 union
1117 {
1118 struct
1119 {
1120 GSRegPMODE PMODE;
1121 uint64 _pad1;
1122 GSRegSMODE1 SMODE1;
1123 uint64 _pad2;
1124 GSRegSMODE2 SMODE2;
1125 uint64 _pad3;
1126 GSRegSRFSH SRFSH;
1127 uint64 _pad4;
1128 GSRegSYNCH1 SYNCH1;
1129 uint64 _pad5;
1130 GSRegSYNCH2 SYNCH2;
1131 uint64 _pad6;
1132 GSRegSYNCV SYNCV;
1133 uint64 _pad7;
1134 struct {
1135 GSRegDISPFB DISPFB;
1136 uint64 _pad1;
1137 GSRegDISPLAY DISPLAY;
1138 uint64 _pad2;
1139 } DISP[2];
1140 GSRegEXTBUF EXTBUF;
1141 uint64 _pad8;
1142 GSRegEXTDATA EXTDATA;
1143 uint64 _pad9;
1144 GSRegEXTWRITE EXTWRITE;
1145 uint64 _pad10;
1146 GSRegBGCOLOR BGCOLOR;
1147 uint64 _pad11;
1148 };
1149
1150 uint8 _pad12[0x1000];
1151 };
1152
1153 union
1154 {
1155 struct
1156 {
1157 GSRegCSR CSR;
1158 uint64 _pad13;
1159 GSRegIMR IMR;
1160 uint64 _pad14;
1161 uint64 _unk1[4];
1162 GSRegBUSDIR BUSDIR;
1163 uint64 _pad15;
1164 uint64 _unk2[6];
1165 GSRegSIGLBLID SIGLBLID;
1166 uint64 _pad16;
1167 };
1168
1169 uint8 _pad17[0x1000];
1170 };
1171 };
1172
1173 #pragma pack(pop)
1174
1175 enum {KEYPRESS=1, KEYRELEASE=2};
1176 struct GSKeyEventData {uint32 key, type;};
1177
1178 enum {FREEZE_LOAD=0, FREEZE_SAVE=1, FREEZE_SIZE=2};
1179 struct GSFreezeData {int size; uint8* data;};
1180
1181 enum stateType {ST_WRITE, ST_TRANSFER, ST_VSYNC};

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