/[pcsx2_0.9.7]/trunk/plugins/GSdx/GS.h
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Contents of /trunk/plugins/GSdx/GS.h

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Revision 31 - (show annotations) (download)
Tue Sep 7 03:24:11 2010 UTC (9 years, 10 months ago) by william
File MIME type: text/plain
File size: 20779 byte(s)
committing r3113 initial commit again...
1 /*
2 * Copyright (C) 2007-2009 Gabest
3 * http://www.gabest.org
4 *
5 * This Program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2, or (at your option)
8 * any later version.
9 *
10 * This Program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with GNU Make; see the file COPYING. If not, write to
17 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
18 * http://www.gnu.org/copyleft/gpl.html
19 *
20 * Special Notes:
21 *
22 * Register definitions and most of the enums originate from sps2dev-0.4.0
23 * Copyright (C) 2002 Terratron Technologies Inc. All Rights Reserved.
24 *
25 */
26
27 #pragma once
28
29 #define PLUGIN_VERSION 16
30
31 #define MAX_PAGES 512
32 #define MAX_BLOCKS 16384
33
34 #include "GSVector.h"
35
36 #pragma pack(push, 1)
37
38 //
39 // sps2registers.h
40 //
41
42 enum GS_PRIM
43 {
44 GS_POINTLIST = 0,
45 GS_LINELIST = 1,
46 GS_LINESTRIP = 2,
47 GS_TRIANGLELIST = 3,
48 GS_TRIANGLESTRIP = 4,
49 GS_TRIANGLEFAN = 5,
50 GS_SPRITE = 6,
51 GS_INVALID = 7,
52 };
53
54 enum GS_PRIM_CLASS
55 {
56 GS_POINT_CLASS = 0,
57 GS_LINE_CLASS = 1,
58 GS_TRIANGLE_CLASS = 2,
59 GS_SPRITE_CLASS = 3,
60 GS_INVALID_CLASS = 7,
61 };
62
63 enum GIF_REG
64 {
65 GIF_REG_PRIM = 0x00,
66 GIF_REG_RGBA = 0x01,
67 GIF_REG_STQ = 0x02,
68 GIF_REG_UV = 0x03,
69 GIF_REG_XYZF2 = 0x04,
70 GIF_REG_XYZ2 = 0x05,
71 GIF_REG_TEX0_1 = 0x06,
72 GIF_REG_TEX0_2 = 0x07,
73 GIF_REG_CLAMP_1 = 0x08,
74 GIF_REG_CLAMP_2 = 0x09,
75 GIF_REG_FOG = 0x0a,
76 GIF_REG_XYZF3 = 0x0c,
77 GIF_REG_XYZ3 = 0x0d,
78 GIF_REG_A_D = 0x0e,
79 GIF_REG_NOP = 0x0f,
80 };
81
82 enum GIF_A_D_REG
83 {
84 GIF_A_D_REG_PRIM = 0x00,
85 GIF_A_D_REG_RGBAQ = 0x01,
86 GIF_A_D_REG_ST = 0x02,
87 GIF_A_D_REG_UV = 0x03,
88 GIF_A_D_REG_XYZF2 = 0x04,
89 GIF_A_D_REG_XYZ2 = 0x05,
90 GIF_A_D_REG_TEX0_1 = 0x06,
91 GIF_A_D_REG_TEX0_2 = 0x07,
92 GIF_A_D_REG_CLAMP_1 = 0x08,
93 GIF_A_D_REG_CLAMP_2 = 0x09,
94 GIF_A_D_REG_FOG = 0x0a,
95 GIF_A_D_REG_XYZF3 = 0x0c,
96 GIF_A_D_REG_XYZ3 = 0x0d,
97 GIF_A_D_REG_NOP = 0x0f,
98 GIF_A_D_REG_TEX1_1 = 0x14,
99 GIF_A_D_REG_TEX1_2 = 0x15,
100 GIF_A_D_REG_TEX2_1 = 0x16,
101 GIF_A_D_REG_TEX2_2 = 0x17,
102 GIF_A_D_REG_XYOFFSET_1 = 0x18,
103 GIF_A_D_REG_XYOFFSET_2 = 0x19,
104 GIF_A_D_REG_PRMODECONT = 0x1a,
105 GIF_A_D_REG_PRMODE = 0x1b,
106 GIF_A_D_REG_TEXCLUT = 0x1c,
107 GIF_A_D_REG_SCANMSK = 0x22,
108 GIF_A_D_REG_MIPTBP1_1 = 0x34,
109 GIF_A_D_REG_MIPTBP1_2 = 0x35,
110 GIF_A_D_REG_MIPTBP2_1 = 0x36,
111 GIF_A_D_REG_MIPTBP2_2 = 0x37,
112 GIF_A_D_REG_TEXA = 0x3b,
113 GIF_A_D_REG_FOGCOL = 0x3d,
114 GIF_A_D_REG_TEXFLUSH = 0x3f,
115 GIF_A_D_REG_SCISSOR_1 = 0x40,
116 GIF_A_D_REG_SCISSOR_2 = 0x41,
117 GIF_A_D_REG_ALPHA_1 = 0x42,
118 GIF_A_D_REG_ALPHA_2 = 0x43,
119 GIF_A_D_REG_DIMX = 0x44,
120 GIF_A_D_REG_DTHE = 0x45,
121 GIF_A_D_REG_COLCLAMP = 0x46,
122 GIF_A_D_REG_TEST_1 = 0x47,
123 GIF_A_D_REG_TEST_2 = 0x48,
124 GIF_A_D_REG_PABE = 0x49,
125 GIF_A_D_REG_FBA_1 = 0x4a,
126 GIF_A_D_REG_FBA_2 = 0x4b,
127 GIF_A_D_REG_FRAME_1 = 0x4c,
128 GIF_A_D_REG_FRAME_2 = 0x4d,
129 GIF_A_D_REG_ZBUF_1 = 0x4e,
130 GIF_A_D_REG_ZBUF_2 = 0x4f,
131 GIF_A_D_REG_BITBLTBUF = 0x50,
132 GIF_A_D_REG_TRXPOS = 0x51,
133 GIF_A_D_REG_TRXREG = 0x52,
134 GIF_A_D_REG_TRXDIR = 0x53,
135 GIF_A_D_REG_HWREG = 0x54,
136 GIF_A_D_REG_SIGNAL = 0x60,
137 GIF_A_D_REG_FINISH = 0x61,
138 GIF_A_D_REG_LABEL = 0x62,
139 };
140
141 enum GIF_FLG
142 {
143 GIF_FLG_PACKED = 0,
144 GIF_FLG_REGLIST = 1,
145 GIF_FLG_IMAGE = 2,
146 GIF_FLG_IMAGE2 = 3
147 };
148
149 enum GS_PSM
150 {
151 PSM_PSMCT32 = 0, // 0000-0000
152 PSM_PSMCT24 = 1, // 0000-0001
153 PSM_PSMCT16 = 2, // 0000-0010
154 PSM_PSMCT16S = 10, // 0000-1010
155 PSM_PSMT8 = 19, // 0001-0011
156 PSM_PSMT4 = 20, // 0001-0100
157 PSM_PSMT8H = 27, // 0001-1011
158 PSM_PSMT4HL = 36, // 0010-0100
159 PSM_PSMT4HH = 44, // 0010-1100
160 PSM_PSMZ32 = 48, // 0011-0000
161 PSM_PSMZ24 = 49, // 0011-0001
162 PSM_PSMZ16 = 50, // 0011-0010
163 PSM_PSMZ16S = 58, // 0011-1010
164 };
165
166 enum GS_TFX
167 {
168 TFX_MODULATE = 0,
169 TFX_DECAL = 1,
170 TFX_HIGHLIGHT = 2,
171 TFX_HIGHLIGHT2 = 3,
172 TFX_NONE = 4,
173 };
174
175 enum GS_CLAMP
176 {
177 CLAMP_REPEAT = 0,
178 CLAMP_CLAMP = 1,
179 CLAMP_REGION_CLAMP = 2,
180 CLAMP_REGION_REPEAT = 3,
181 };
182
183 enum GS_ZTST
184 {
185 ZTST_NEVER = 0,
186 ZTST_ALWAYS = 1,
187 ZTST_GEQUAL = 2,
188 ZTST_GREATER = 3,
189 };
190
191 enum GS_ATST
192 {
193 ATST_NEVER = 0,
194 ATST_ALWAYS = 1,
195 ATST_LESS = 2,
196 ATST_LEQUAL = 3,
197 ATST_EQUAL = 4,
198 ATST_GEQUAL = 5,
199 ATST_GREATER = 6,
200 ATST_NOTEQUAL = 7,
201 };
202
203 enum GS_AFAIL
204 {
205 AFAIL_KEEP = 0,
206 AFAIL_FB_ONLY = 1,
207 AFAIL_ZB_ONLY = 2,
208 AFAIL_RGB_ONLY = 3,
209 };
210
211 //
212 // sps2regstructs.h
213 //
214
215 #define REG32(name) \
216 union name \
217 { \
218 uint32 u32; \
219 struct { \
220
221 #define REG64(name) \
222 union name \
223 { \
224 uint64 u64; \
225 uint32 u32[2]; \
226 void operator = (const GSVector4i& v) {GSVector4i::storel(this, v);} \
227 bool operator == (const union name& r) const {return ((GSVector4i)r).eq(*this);} \
228 bool operator != (const union name& r) const {return !((GSVector4i)r).eq(*this);} \
229 operator GSVector4i() const {return GSVector4i::loadl(this);} \
230 struct { \
231
232 #define REG128(name)\
233 union name \
234 { \
235 uint64 u64[2]; \
236 uint32 u32[4]; \
237 struct { \
238
239 #define REG32_(prefix, name) REG32(prefix##name)
240 #define REG64_(prefix, name) REG64(prefix##name)
241 #define REG128_(prefix, name) REG128(prefix##name)
242
243 #define REG_END }; };
244 #define REG_END2 };
245
246 #define REG32_SET(name) \
247 union name \
248 { \
249 uint32 u32; \
250
251 #define REG64_SET(name) \
252 union name \
253 { \
254 uint64 u64; \
255 uint32 u32[2]; \
256
257 #define REG128_SET(name)\
258 union name \
259 { \
260 __m128i m128; \
261 uint64 u64[2]; \
262 uint32 u32[4]; \
263
264 #define REG_SET_END };
265
266 REG64_(GSReg, BGCOLOR)
267 uint32 R:8;
268 uint32 G:8;
269 uint32 B:8;
270 uint32 _PAD1:8;
271 uint32 _PAD2:32;
272 REG_END
273
274 REG64_(GSReg, BUSDIR)
275 uint32 DIR:1;
276 uint32 _PAD1:31;
277 uint32 _PAD2:32;
278 REG_END
279
280 REG64_(GSReg, CSR)
281 uint32 rSIGNAL:1;
282 uint32 rFINISH:1;
283 uint32 rHSINT:1;
284 uint32 rVSINT:1;
285 uint32 rEDWINT:1;
286 uint32 rZERO1:1;
287 uint32 rZERO2:1;
288 uint32 r_PAD1:1;
289 uint32 rFLUSH:1;
290 uint32 rRESET:1;
291 uint32 r_PAD2:2;
292 uint32 rNFIELD:1;
293 uint32 rFIELD:1;
294 uint32 rFIFO:2;
295 uint32 rREV:8;
296 uint32 rID:8;
297 uint32 wSIGNAL:1;
298 uint32 wFINISH:1;
299 uint32 wHSINT:1;
300 uint32 wVSINT:1;
301 uint32 wEDWINT:1;
302 uint32 wZERO1:1;
303 uint32 wZERO2:1;
304 uint32 w_PAD1:1;
305 uint32 wFLUSH:1;
306 uint32 wRESET:1;
307 uint32 w_PAD2:2;
308 uint32 wNFIELD:1;
309 uint32 wFIELD:1;
310 uint32 wFIFO:2;
311 uint32 wREV:8;
312 uint32 wID:8;
313 REG_END
314
315 REG64_(GSReg, DISPFB) // (-1/2)
316 uint32 FBP:9;
317 uint32 FBW:6;
318 uint32 PSM:5;
319 uint32 _PAD:12;
320 uint32 DBX:11;
321 uint32 DBY:11;
322 uint32 _PAD2:10;
323 REG_END2
324 uint32 Block() const {return FBP << 5;}
325 REG_END2
326
327 REG64_(GSReg, DISPLAY) // (-1/2)
328 uint32 DX:12;
329 uint32 DY:11;
330 uint32 MAGH:4;
331 uint32 MAGV:2;
332 uint32 _PAD:3;
333 uint32 DW:12;
334 uint32 DH:11;
335 uint32 _PAD2:9;
336 REG_END
337
338 REG64_(GSReg, EXTBUF)
339 uint32 EXBP:14;
340 uint32 EXBW:6;
341 uint32 FBIN:2;
342 uint32 WFFMD:1;
343 uint32 EMODA:2;
344 uint32 EMODC:2;
345 uint32 _PAD1:5;
346 uint32 WDX:11;
347 uint32 WDY:11;
348 uint32 _PAD2:10;
349 REG_END
350
351 REG64_(GSReg, EXTDATA)
352 uint32 SX:12;
353 uint32 SY:11;
354 uint32 SMPH:4;
355 uint32 SMPV:2;
356 uint32 _PAD1:3;
357 uint32 WW:12;
358 uint32 WH:11;
359 uint32 _PAD2:9;
360 REG_END
361
362 REG64_(GSReg, EXTWRITE)
363 uint32 WRITE:1;
364 uint32 _PAD1:31;
365 uint32 _PAD2:32;
366 REG_END
367
368 REG64_(GSReg, IMR)
369 uint32 _PAD1:8;
370 uint32 SIGMSK:1;
371 uint32 FINISHMSK:1;
372 uint32 HSMSK:1;
373 uint32 VSMSK:1;
374 uint32 EDWMSK:1;
375 uint32 _PAD2:19;
376 uint32 _PAD3:32;
377 REG_END
378
379 REG64_(GSReg, PMODE)
380 union
381 {
382 struct
383 {
384 uint32 EN1:1;
385 uint32 EN2:1;
386 uint32 CRTMD:3;
387 uint32 MMOD:1;
388 uint32 AMOD:1;
389 uint32 SLBG:1;
390 uint32 ALP:8;
391 uint32 _PAD:16;
392 uint32 _PAD1:32;
393 };
394
395 struct
396 {
397 uint32 EN:2;
398 uint32 _PAD2:30;
399 uint32 _PAD3:32;
400 };
401 };
402 REG_END
403
404 REG64_(GSReg, SIGLBLID)
405 uint32 SIGID:32;
406 uint32 LBLID:32;
407 REG_END
408
409 REG64_(GSReg, SMODE1)
410 uint32 RC:3;
411 uint32 LC:7;
412 uint32 T1248:2;
413 uint32 SLCK:1;
414 uint32 CMOD:2;
415 uint32 EX:1;
416 uint32 PRST:1;
417 uint32 SINT:1;
418 uint32 XPCK:1;
419 uint32 PCK2:2;
420 uint32 SPML:4;
421 uint32 GCONT:1; // YCrCb
422 uint32 PHS:1;
423 uint32 PVS:1;
424 uint32 PEHS:1;
425 uint32 PEVS:1;
426 uint32 CLKSEL:2;
427 uint32 NVCK:1;
428 uint32 SLCK2:1;
429 uint32 VCKSEL:2;
430 uint32 VHP:1;
431 uint32 _PAD1:27;
432 REG_END
433
434 /*
435
436 // pal
437
438 CLKSEL=1 CMOD=3 EX=0 GCONT=0 LC=32 NVCK=1 PCK2=0 PEHS=0 PEVS=0 PHS=0 PRST=1 PVS=0 RC=4 SINT=0 SLCK=0 SLCK2=1 SPML=4 T1248=1 VCKSEL=1 VHP=0 XPCK=0
439
440 // ntsc
441
442 CLKSEL=1 CMOD=2 EX=0 GCONT=0 LC=32 NVCK=1 PCK2=0 PEHS=0 PEVS=0 PHS=0 PRST=1 PVS=0 RC=4 SINT=0 SLCK=0 SLCK2=1 SPML=4 T1248=1 VCKSEL=1 VHP=0 XPCK=0
443
444 // ntsc progressive (SoTC)
445
446 CLKSEL=1 CMOD=0 EX=0 GCONT=0 LC=32 NVCK=1 PCK2=0 PEHS=0 PEVS=0 PHS=0 PRST=1 PVS=0 RC=4 SINT=0 SLCK=0 SLCK2=1 SPML=2 T1248=1 VCKSEL=1 VHP=1 XPCK=0
447
448 */
449
450 REG64_(GSReg, SMODE2)
451 uint32 INT:1;
452 uint32 FFMD:1;
453 uint32 DPMS:2;
454 uint32 _PAD2:28;
455 uint32 _PAD3:32;
456 REG_END
457
458 REG64_(GSReg, SRFSH)
459 uint32 _DUMMY;
460 // TODO
461 REG_END
462
463 REG64_(GSReg, SYNCH1)
464 uint32 _DUMMY;
465 // TODO
466 REG_END
467
468 REG64_(GSReg, SYNCH2)
469 uint32 _DUMMY;
470 // TODO
471 REG_END
472
473 REG64_(GSReg, SYNCV)
474 uint64 _DUMMY;
475 // TODO
476 REG_END
477
478 REG64_SET(GSReg)
479 GSRegBGCOLOR BGCOLOR;
480 GSRegBUSDIR BUSDIR;
481 GSRegCSR CSR;
482 GSRegDISPFB DISPFB;
483 GSRegDISPLAY DISPLAY;
484 GSRegEXTBUF EXTBUF;
485 GSRegEXTDATA EXTDATA;
486 GSRegEXTWRITE EXTWRITE;
487 GSRegIMR IMR;
488 GSRegPMODE PMODE;
489 GSRegSIGLBLID SIGLBLID;
490 GSRegSMODE1 SMODE1;
491 GSRegSMODE2 SMODE2;
492 REG_SET_END
493
494 //
495 // sps2tags.h
496 //
497
498 #define SET_GIF_REG(gifTag, iRegNo, uiValue) \
499 {((GIFTag*)&gifTag)->u64[1] |= (((uiValue) & 0xf) << ((iRegNo) << 2));}
500
501 #ifdef _M_AMD64
502 #define GET_GIF_REG(tag, reg) \
503 (((tag).u64[1] >> ((reg) << 2)) & 0xf)
504 #else
505 #define GET_GIF_REG(tag, reg) \
506 (((tag).u32[2 + ((reg) >> 3)] >> (((reg) & 7) << 2)) & 0xf)
507 #endif
508
509 //
510 // GIFTag
511
512 REG128(GIFTag)
513 uint32 NLOOP:15;
514 uint32 EOP:1;
515 uint32 _PAD1:16;
516 uint32 _PAD2:14;
517 uint32 PRE:1;
518 uint32 PRIM:11;
519 uint32 FLG:2; // enum GIF_FLG
520 uint32 NREG:4;
521 uint64 REGS:64;
522 REG_END
523
524 // GIFReg
525
526 REG64_(GIFReg, ALPHA)
527 uint32 A:2;
528 uint32 B:2;
529 uint32 C:2;
530 uint32 D:2;
531 uint32 _PAD1:24;
532 uint32 FIX:8;
533 uint32 _PAD2:24;
534 REG_END2
535 // opaque => output will be Cs/As
536 __forceinline bool IsOpaque() const {return (A == B || C == 2 && FIX == 0) && D == 0 || (A == 0 && B == D && C == 2 && FIX == 0x80);}
537 __forceinline bool IsOpaque(int amin, int amax) const {return (A == B || amax == 0) && D == 0 || A == 0 && B == D && amin == 0x80 && amax == 0x80;}
538 REG_END2
539
540 REG64_(GIFReg, BITBLTBUF)
541 uint32 SBP:14;
542 uint32 _PAD1:2;
543 uint32 SBW:6;
544 uint32 _PAD2:2;
545 uint32 SPSM:6;
546 uint32 _PAD3:2;
547 uint32 DBP:14;
548 uint32 _PAD4:2;
549 uint32 DBW:6;
550 uint32 _PAD5:2;
551 uint32 DPSM:6;
552 uint32 _PAD6:2;
553 REG_END
554
555 REG64_(GIFReg, CLAMP)
556 union
557 {
558 struct
559 {
560 uint32 WMS:2;
561 uint32 WMT:2;
562 uint32 MINU:10;
563 uint32 MAXU:10;
564 uint32 _PAD1:8;
565 uint32 _PAD2:2;
566 uint32 MAXV:10;
567 uint32 _PAD3:20;
568 };
569
570 struct
571 {
572 uint64 _PAD4:24;
573 uint64 MINV:10;
574 uint64 _PAD5:30;
575 };
576 };
577 REG_END
578
579 REG64_(GIFReg, COLCLAMP)
580 uint32 CLAMP:1;
581 uint32 _PAD1:31;
582 uint32 _PAD2:32;
583 REG_END
584
585 REG64_(GIFReg, DIMX)
586 int32 DM00:3;
587 int32 _PAD00:1;
588 int32 DM01:3;
589 int32 _PAD01:1;
590 int32 DM02:3;
591 int32 _PAD02:1;
592 int32 DM03:3;
593 int32 _PAD03:1;
594 int32 DM10:3;
595 int32 _PAD10:1;
596 int32 DM11:3;
597 int32 _PAD11:1;
598 int32 DM12:3;
599 int32 _PAD12:1;
600 int32 DM13:3;
601 int32 _PAD13:1;
602 int32 DM20:3;
603 int32 _PAD20:1;
604 int32 DM21:3;
605 int32 _PAD21:1;
606 int32 DM22:3;
607 int32 _PAD22:1;
608 int32 DM23:3;
609 int32 _PAD23:1;
610 int32 DM30:3;
611 int32 _PAD30:1;
612 int32 DM31:3;
613 int32 _PAD31:1;
614 int32 DM32:3;
615 int32 _PAD32:1;
616 int32 DM33:3;
617 int32 _PAD33:1;
618 REG_END
619
620 REG64_(GIFReg, DTHE)
621 uint32 DTHE:1;
622 uint32 _PAD1:31;
623 uint32 _PAD2:32;
624 REG_END
625
626 REG64_(GIFReg, FBA)
627 uint32 FBA:1;
628 uint32 _PAD1:31;
629 uint32 _PAD2:32;
630 REG_END
631
632 REG64_(GIFReg, FINISH)
633 uint32 _PAD1:32;
634 uint32 _PAD2:32;
635 REG_END
636
637 REG64_(GIFReg, FOG)
638 uint32 _PAD1:32;
639 uint32 _PAD2:24;
640 uint32 F:8;
641 REG_END
642
643 REG64_(GIFReg, FOGCOL)
644 uint32 FCR:8;
645 uint32 FCG:8;
646 uint32 FCB:8;
647 uint32 _PAD1:8;
648 uint32 _PAD2:32;
649 REG_END
650
651 REG64_(GIFReg, FRAME)
652 uint32 FBP:9;
653 uint32 _PAD1:7;
654 uint32 FBW:6;
655 uint32 _PAD2:2;
656 uint32 PSM:6;
657 uint32 _PAD3:2;
658 uint32 FBMSK:32;
659 REG_END2
660 uint32 Block() const {return FBP << 5;}
661 REG_END2
662
663 REG64_(GIFReg, HWREG)
664 uint32 DATA_LOWER:32;
665 uint32 DATA_UPPER:32;
666 REG_END
667
668 REG64_(GIFReg, LABEL)
669 uint32 ID:32;
670 uint32 IDMSK:32;
671 REG_END
672
673 REG64_(GIFReg, MIPTBP1)
674 uint64 TBP1:14;
675 uint64 TBW1:6;
676 uint64 TBP2:14;
677 uint64 TBW2:6;
678 uint64 TBP3:14;
679 uint64 TBW3:6;
680 uint64 _PAD:4;
681 REG_END
682
683 REG64_(GIFReg, MIPTBP2)
684 uint64 TBP4:14;
685 uint64 TBW4:6;
686 uint64 TBP5:14;
687 uint64 TBW5:6;
688 uint64 TBP6:14;
689 uint64 TBW6:6;
690 uint64 _PAD:4;
691 REG_END
692
693 REG64_(GIFReg, NOP)
694 uint32 _PAD1:32;
695 uint32 _PAD2:32;
696 REG_END
697
698 REG64_(GIFReg, PABE)
699 uint32 PABE:1;
700 uint32 _PAD1:31;
701 uint32 _PAD2:32;
702 REG_END
703
704 REG64_(GIFReg, PRIM)
705 uint32 PRIM:3;
706 uint32 IIP:1;
707 uint32 TME:1;
708 uint32 FGE:1;
709 uint32 ABE:1;
710 uint32 AA1:1;
711 uint32 FST:1;
712 uint32 CTXT:1;
713 uint32 FIX:1;
714 uint32 _PAD1:21;
715 uint32 _PAD2:32;
716 REG_END
717
718 REG64_(GIFReg, PRMODE)
719 uint32 _PRIM:3;
720 uint32 IIP:1;
721 uint32 TME:1;
722 uint32 FGE:1;
723 uint32 ABE:1;
724 uint32 AA1:1;
725 uint32 FST:1;
726 uint32 CTXT:1;
727 uint32 FIX:1;
728 uint32 _PAD2:21;
729 uint32 _PAD3:32;
730 REG_END
731
732 REG64_(GIFReg, PRMODECONT)
733 uint32 AC:1;
734 uint32 _PAD1:31;
735 uint32 _PAD2:32;
736 REG_END
737
738 REG64_(GIFReg, RGBAQ)
739 uint32 R:8;
740 uint32 G:8;
741 uint32 B:8;
742 uint32 A:8;
743 float Q;
744 REG_END
745
746 REG64_(GIFReg, SCANMSK)
747 uint32 MSK:2;
748 uint32 _PAD1:30;
749 uint32 _PAD2:32;
750 REG_END
751
752 REG64_(GIFReg, SCISSOR)
753 uint32 SCAX0:11;
754 uint32 _PAD1:5;
755 uint32 SCAX1:11;
756 uint32 _PAD2:5;
757 uint32 SCAY0:11;
758 uint32 _PAD3:5;
759 uint32 SCAY1:11;
760 uint32 _PAD4:5;
761 REG_END
762
763 REG64_(GIFReg, SIGNAL)
764 uint32 ID:32;
765 uint32 IDMSK:32;
766 REG_END
767
768 REG64_(GIFReg, ST)
769 float S;
770 float T;
771 REG_END
772
773 REG64_(GIFReg, TEST)
774 uint32 ATE:1;
775 uint32 ATST:3;
776 uint32 AREF:8;
777 uint32 AFAIL:2;
778 uint32 DATE:1;
779 uint32 DATM:1;
780 uint32 ZTE:1;
781 uint32 ZTST:2;
782 uint32 _PAD1:13;
783 uint32 _PAD2:32;
784 REG_END2
785 __forceinline bool DoFirstPass() {return !ATE || ATST != ATST_NEVER;} // not all pixels fail automatically
786 __forceinline bool DoSecondPass() {return ATE && ATST != ATST_ALWAYS && AFAIL != AFAIL_KEEP;} // pixels may fail, write fb/z
787 __forceinline bool NoSecondPass() {return ATE && ATST != ATST_ALWAYS && AFAIL == AFAIL_KEEP;} // pixels may fail, no output
788 REG_END2
789
790 REG64_(GIFReg, TEX0)
791 union
792 {
793 struct
794 {
795 uint32 TBP0:14;
796 uint32 TBW:6;
797 uint32 PSM:6;
798 uint32 TW:4;
799 uint32 _PAD1:2;
800 uint32 _PAD2:2;
801 uint32 TCC:1;
802 uint32 TFX:2;
803 uint32 CBP:14;
804 uint32 CPSM:4;
805 uint32 CSM:1;
806 uint32 CSA:5;
807 uint32 CLD:3;
808 };
809
810 struct
811 {
812 uint64 _PAD3:30;
813 uint64 TH:4;
814 uint64 _PAD4:30;
815 };
816 };
817 REG_END2
818 __forceinline bool IsRepeating() {return ((uint32)1 << TW) > (TBW << 6);}
819 REG_END2
820
821 REG64_(GIFReg, TEX1)
822 uint32 LCM:1;
823 uint32 _PAD1:1;
824 uint32 MXL:3;
825 uint32 MMAG:1;
826 uint32 MMIN:3;
827 uint32 MTBA:1;
828 uint32 _PAD2:9;
829 uint32 L:2;
830 uint32 _PAD3:11;
831 int32 K:12; // 1:7:4
832 uint32 _PAD4:20;
833 REG_END2
834 bool IsMinLinear() const {return (MMIN == 1) || (MMIN & 4);}
835 bool IsMagLinear() const {return MMAG;}
836 REG_END2
837
838 REG64_(GIFReg, TEX2)
839 uint32 _PAD1:20;
840 uint32 PSM:6;
841 uint32 _PAD2:6;
842 uint32 _PAD3:5;
843 uint32 CBP:14;
844 uint32 CPSM:4;
845 uint32 CSM:1;
846 uint32 CSA:5;
847 uint32 CLD:3;
848 REG_END
849
850 REG64_(GIFReg, TEXA)
851 uint32 TA0:8;
852 uint32 _PAD1:7;
853 uint32 AEM:1;
854 uint32 _PAD2:16;
855 uint32 TA1:8;
856 uint32 _PAD3:24;
857 REG_END
858
859 REG64_(GIFReg, TEXCLUT)
860 uint32 CBW:6;
861 uint32 COU:6;
862 uint32 COV:10;
863 uint32 _PAD1:10;
864 uint32 _PAD2:32;
865 REG_END
866
867 REG64_(GIFReg, TEXFLUSH)
868 uint32 _PAD1:32;
869 uint32 _PAD2:32;
870 REG_END
871
872 REG64_(GIFReg, TRXDIR)
873 uint32 XDIR:2;
874 uint32 _PAD1:30;
875 uint32 _PAD2:32;
876 REG_END
877
878 REG64_(GIFReg, TRXPOS)
879 uint32 SSAX:11;
880 uint32 _PAD1:5;
881 uint32 SSAY:11;
882 uint32 _PAD2:5;
883 uint32 DSAX:11;
884 uint32 _PAD3:5;
885 uint32 DSAY:11;
886 uint32 DIRY:1;
887 uint32 DIRX:1;
888 uint32 _PAD4:3;
889 REG_END
890
891 REG64_(GIFReg, TRXREG)
892 uint32 RRW:12;
893 uint32 _PAD1:20;
894 uint32 RRH:12;
895 uint32 _PAD2:20;
896 REG_END
897
898 // GSState::GIFPackedRegHandlerUV and GSState::GIFRegHandlerUV will make sure that the _PAD1/2 bits are set to zero
899
900 REG64_(GIFReg, UV)
901 uint32 U:16;
902 // uint32 _PAD1:2;
903 uint32 V:16;
904 // uint32 _PAD2:2;
905 uint32 _PAD3:32;
906 REG_END
907
908 // GSState::GIFRegHandlerXYOFFSET will make sure that the _PAD1/2 bits are set to zero
909
910 REG64_(GIFReg, XYOFFSET)
911 uint32 OFX; // :16; uint32 _PAD1:16;
912 uint32 OFY; // :16; uint32 _PAD2:16;
913 REG_END
914
915 REG64_(GIFReg, XYZ)
916 uint32 X:16;
917 uint32 Y:16;
918 uint32 Z:32;
919 REG_END
920
921 REG64_(GIFReg, XYZF)
922 uint32 X:16;
923 uint32 Y:16;
924 uint32 Z:24;
925 uint32 F:8;
926 REG_END
927
928 REG64_(GIFReg, ZBUF)
929 uint32 ZBP:9;
930 uint32 _PAD1:15;
931 // uint32 PSM:4;
932 // uint32 _PAD2:4;
933 uint32 PSM:6;
934 uint32 _PAD2:2;
935 uint32 ZMSK:1;
936 uint32 _PAD3:31;
937 REG_END2
938 uint32 Block() const {return ZBP << 5;}
939 REG_END2
940
941 REG64_SET(GIFReg)
942 GIFRegALPHA ALPHA;
943 GIFRegBITBLTBUF BITBLTBUF;
944 GIFRegCLAMP CLAMP;
945 GIFRegCOLCLAMP COLCLAMP;
946 GIFRegDIMX DIMX;
947 GIFRegDTHE DTHE;
948 GIFRegFBA FBA;
949 GIFRegFINISH FINISH;
950 GIFRegFOG FOG;
951 GIFRegFOGCOL FOGCOL;
952 GIFRegFRAME FRAME;
953 GIFRegHWREG HWREG;
954 GIFRegLABEL LABEL;
955 GIFRegMIPTBP1 MIPTBP1;
956 GIFRegMIPTBP2 MIPTBP2;
957 GIFRegNOP NOP;
958 GIFRegPABE PABE;
959 GIFRegPRIM PRIM;
960 GIFRegPRMODE PRMODE;
961 GIFRegPRMODECONT PRMODECONT;
962 GIFRegRGBAQ RGBAQ;
963 GIFRegSCANMSK SCANMSK;
964 GIFRegSCISSOR SCISSOR;
965 GIFRegSIGNAL SIGNAL;
966 GIFRegST ST;
967 GIFRegTEST TEST;
968 GIFRegTEX0 TEX0;
969 GIFRegTEX1 TEX1;
970 GIFRegTEX2 TEX2;
971 GIFRegTEXA TEXA;
972 GIFRegTEXCLUT TEXCLUT;
973 GIFRegTEXFLUSH TEXFLUSH;
974 GIFRegTRXDIR TRXDIR;
975 GIFRegTRXPOS TRXPOS;
976 GIFRegTRXREG TRXREG;
977 GIFRegUV UV;
978 GIFRegXYOFFSET XYOFFSET;
979 GIFRegXYZ XYZ;
980 GIFRegXYZF XYZF;
981 GIFRegZBUF ZBUF;
982 REG_SET_END
983
984 // GIFPacked
985
986 REG128_(GIFPacked, PRIM)
987 uint32 PRIM:11;
988 uint32 _PAD1:21;
989 uint32 _PAD2:32;
990 uint32 _PAD3:32;
991 uint32 _PAD4:32;
992 REG_END
993
994 REG128_(GIFPacked, RGBA)
995 uint32 R:8;
996 uint32 _PAD1:24;
997 uint32 G:8;
998 uint32 _PAD2:24;
999 uint32 B:8;
1000 uint32 _PAD3:24;
1001 uint32 A:8;
1002 uint32 _PAD4:24;
1003 REG_END
1004
1005 REG128_(GIFPacked, STQ)
1006 float S;
1007 float T;
1008 float Q;
1009 uint32 _PAD1:32;
1010 REG_END
1011
1012 REG128_(GIFPacked, UV)
1013 uint32 U:14;
1014 uint32 _PAD1:18;
1015 uint32 V:14;
1016 uint32 _PAD2:18;
1017 uint32 _PAD3:32;
1018 uint32 _PAD4:32;
1019 REG_END
1020
1021 REG128_(GIFPacked, XYZF2)
1022 uint32 X:16;
1023 uint32 _PAD1:16;
1024 uint32 Y:16;
1025 uint32 _PAD2:16;
1026 uint32 _PAD3:4;
1027 uint32 Z:24;
1028 uint32 _PAD4:4;
1029 uint32 _PAD5:4;
1030 uint32 F:8;
1031 uint32 _PAD6:3;
1032 uint32 ADC:1;
1033 uint32 _PAD7:16;
1034 REG_END
1035
1036 REG128_(GIFPacked, XYZ2)
1037 uint32 X:16;
1038 uint32 _PAD1:16;
1039 uint32 Y:16;
1040 uint32 _PAD2:16;
1041 uint32 Z:32;
1042 uint32 _PAD3:15;
1043 uint32 ADC:1;
1044 uint32 _PAD4:16;
1045 REG_END
1046
1047 REG128_(GIFPacked, FOG)
1048 uint32 _PAD1:32;
1049 uint32 _PAD2:32;
1050 uint32 _PAD3:32;
1051 uint32 _PAD4:4;
1052 uint32 F:8;
1053 uint32 _PAD5:20;
1054 REG_END
1055
1056 REG128_(GIFPacked, A_D)
1057 uint64 DATA:64;
1058 uint32 ADDR:8; // enum GIF_A_D_REG
1059 uint32 _PAD1:24;
1060 uint32 _PAD2:32;
1061 REG_END
1062
1063 REG128_(GIFPacked, NOP)
1064 uint32 _PAD1:32;
1065 uint32 _PAD2:32;
1066 uint32 _PAD3:32;
1067 uint32 _PAD4:32;
1068 REG_END
1069
1070 REG128_SET(GIFPackedReg)
1071 GIFReg r;
1072 GIFPackedPRIM PRIM;
1073 GIFPackedRGBA RGBA;
1074 GIFPackedSTQ STQ;
1075 GIFPackedUV UV;
1076 GIFPackedXYZF2 XYZF2;
1077 GIFPackedXYZ2 XYZ2;
1078 GIFPackedFOG FOG;
1079 GIFPackedA_D A_D;
1080 GIFPackedNOP NOP;
1081 REG_SET_END
1082
1083 __aligned16 struct GIFPath
1084 {
1085 GIFTag tag;
1086 uint32 reg;
1087 uint32 nreg;
1088 uint32 nloop;
1089 uint32 adonly;
1090 GSVector4i regs;
1091
1092 void SetTag(const void* mem)
1093 {
1094 GSVector4i v = GSVector4i::load<false>(mem);
1095 GSVector4i::store<true>(&tag, v);
1096 reg = 0;
1097 regs = v.uph8(v >> 4) & 0x0f0f0f0f;
1098 nreg = tag.NREG;
1099 nloop = tag.NLOOP;
1100 adonly = nreg == 1 && regs.u8[0] == GIF_REG_A_D;
1101 }
1102
1103 __forceinline uint8 GetReg()
1104 {
1105 return regs.u8[reg]; // GET_GIF_REG(tag, reg);
1106 }
1107
1108 __forceinline bool StepReg()
1109 {
1110 if((++reg & 0xf) == nreg)
1111 {
1112 reg = 0;
1113 if(--nloop == 0)
1114 return false;
1115 }
1116
1117 return true;
1118 }
1119 };
1120
1121 struct GSPrivRegSet
1122 {
1123 union
1124 {
1125 struct
1126 {
1127 GSRegPMODE PMODE;
1128 uint64 _pad1;
1129 GSRegSMODE1 SMODE1;
1130 uint64 _pad2;
1131 GSRegSMODE2 SMODE2;
1132 uint64 _pad3;
1133 GSRegSRFSH SRFSH;
1134 uint64 _pad4;
1135 GSRegSYNCH1 SYNCH1;
1136 uint64 _pad5;
1137 GSRegSYNCH2 SYNCH2;
1138 uint64 _pad6;
1139 GSRegSYNCV SYNCV;
1140 uint64 _pad7;
1141 struct {
1142 GSRegDISPFB DISPFB;
1143 uint64 _pad1;
1144 GSRegDISPLAY DISPLAY;
1145 uint64 _pad2;
1146 } DISP[2];
1147 GSRegEXTBUF EXTBUF;
1148 uint64 _pad8;
1149 GSRegEXTDATA EXTDATA;
1150 uint64 _pad9;
1151 GSRegEXTWRITE EXTWRITE;
1152 uint64 _pad10;
1153 GSRegBGCOLOR BGCOLOR;
1154 uint64 _pad11;
1155 };
1156
1157 uint8 _pad12[0x1000];
1158 };
1159
1160 union
1161 {
1162 struct
1163 {
1164 GSRegCSR CSR;
1165 uint64 _pad13;
1166 GSRegIMR IMR;
1167 uint64 _pad14;
1168 uint64 _unk1[4];
1169 GSRegBUSDIR BUSDIR;
1170 uint64 _pad15;
1171 uint64 _unk2[6];
1172 GSRegSIGLBLID SIGLBLID;
1173 uint64 _pad16;
1174 };
1175
1176 uint8 _pad17[0x1000];
1177 };
1178 };
1179
1180 #pragma pack(pop)
1181
1182 enum {KEYPRESS=1, KEYRELEASE=2};
1183 struct GSKeyEventData {uint32 key, type;};
1184
1185 enum {FREEZE_LOAD=0, FREEZE_SAVE=1, FREEZE_SIZE=2};
1186 struct GSFreezeData {int size; uint8* data;};
1187
1188 enum stateType {ST_WRITE, ST_TRANSFER, ST_VSYNC};

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