/[pcsx2_0.9.7]/trunk/pcsx2/ps2/LegacyDmac.cpp
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Diff of /trunk/pcsx2/ps2/LegacyDmac.cpp

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--- trunk/pcsx2/ps2/LegacyDmac.cpp	2010/12/23 11:48:33	279
+++ trunk/pcsx2/ps2/LegacyDmac.cpp	2010/12/23 12:02:12	280
@@ -104,7 +104,7 @@
 	// FIXME: Why??? DMA uses physical addresses
 	addr &= 0x1ffffff0;
 
-	if (addr < Ps2MemSize::Base)
+	if (addr < Ps2MemSize::MainRam)
 	{
 		return (tDMA_TAG*)&eeMem->Main[addr];
 	}
@@ -133,7 +133,7 @@
 	// FIXME: Why??? DMA uses physical addresses
 	addr &= 0x1ffffff0;
 
-	if (addr < Ps2MemSize::Base)
+	if (addr < Ps2MemSize::MainRam)
 	{
 		return (tDMA_TAG*)&eeMem->Main[addr];
 	}
@@ -292,125 +292,151 @@
 __fi bool dmacWrite32( u32 mem, mem32_t& value )
 {
 	iswitch(mem) {
-	icase(D0_CHCR) // dma0 - vif0
-	{
-		DMA_LOG("VIF0dma EXECUTE, value=0x%x", value);
-		DmaExec(dmaVIF0, mem, value);
-		return false;
-	}
-
-	icase(D1_CHCR) // dma1 - vif1 - chcr
-	{
-		DMA_LOG("VIF1dma EXECUTE, value=0x%x", value);
-		DmaExec(dmaVIF1, mem, value);
-		return false;
-	}
-
-	icase(D2_CHCR) // dma2 - gif
-	{
-		DMA_LOG("GIFdma EXECUTE, value=0x%x", value);
-		DmaExec(dmaGIF, mem, value);
-		return false;
-	}
+		icase(D0_CHCR) // dma0 - vif0
+		{
+			DMA_LOG("VIF0dma EXECUTE, value=0x%x", value);
+			DmaExec(dmaVIF0, mem, value);
+			return false;
+		}
 
-	icase(D3_CHCR) // dma3 - fromIPU
-	{
-		DMA_LOG("IPU0dma EXECUTE, value=0x%x\n", value);
-		DmaExec(dmaIPU0, mem, value);
-		return false;
-	}
+		icase(D1_CHCR) // dma1 - vif1 - chcr
+		{
+			DMA_LOG("VIF1dma EXECUTE, value=0x%x", value);
+			DmaExec(dmaVIF1, mem, value);
+			return false;
+		}
 
-	icase(D4_CHCR) // dma4 - toIPU
-	{
-		DMA_LOG("IPU1dma EXECUTE, value=0x%x\n", value);
-		DmaExec(dmaIPU1, mem, value);
-		return false;
-	}
+		icase(D2_CHCR) // dma2 - gif
+		{
+			DMA_LOG("GIFdma EXECUTE, value=0x%x", value);
+			DmaExec(dmaGIF, mem, value);
+			return false;
+		}
 
-	icase(D5_CHCR) // dma5 - sif0
-	{
-		DMA_LOG("SIF0dma EXECUTE, value=0x%x", value);
-		DmaExec(dmaSIF0, mem, value);
-		return false;
-	}
+		icase(D3_CHCR) // dma3 - fromIPU
+		{
+			DMA_LOG("IPU0dma EXECUTE, value=0x%x\n", value);
+			DmaExec(dmaIPU0, mem, value);
+			return false;
+		}
 
-	icase(D6_CHCR) // dma6 - sif1
-	{
-		DMA_LOG("SIF1dma EXECUTE, value=0x%x", value);
-		DmaExec(dmaSIF1, mem, value);
-		return false;
-	}
+		icase(D4_CHCR) // dma4 - toIPU
+		{
+			DMA_LOG("IPU1dma EXECUTE, value=0x%x\n", value);
+			DmaExec(dmaIPU1, mem, value);
+			return false;
+		}
 
-	icase(D7_CHCR) // dma7 - sif2
-	{
-		DMA_LOG("SIF2dma EXECUTE, value=0x%x", value);
-		DmaExec(dmaSIF2, mem, value);
-		return false;
-	}
+		icase(D5_CHCR) // dma5 - sif0
+		{
+			DMA_LOG("SIF0dma EXECUTE, value=0x%x", value);
+			DmaExec(dmaSIF0, mem, value);
+			return false;
+		}
 
-	icase(D8_CHCR) // dma8 - fromSPR
-	{
-		DMA_LOG("SPR0dma EXECUTE (fromSPR), value=0x%x", value);
-		DmaExec(dmaSPR0, mem, value);
-		return false;
-	}
+		icase(D6_CHCR) // dma6 - sif1
+		{
+			DMA_LOG("SIF1dma EXECUTE, value=0x%x", value);
+			DmaExec(dmaSIF1, mem, value);
+			return false;
+		}
 
-	icase(D9_CHCR) // dma9 - toSPR
-	{
-		DMA_LOG("SPR1dma EXECUTE (toSPR), value=0x%x", value);
-		DmaExec(dmaSPR1, mem, value);
-		return false;
-	}
-		
-	icase(DMAC_CTRL)
-	{
-		u32 oldvalue = psHu32(mem);
+		icase(D7_CHCR) // dma7 - sif2
+		{
+			DMA_LOG("SIF2dma EXECUTE, value=0x%x", value);
+			DmaExec(dmaSIF2, mem, value);
+			return false;
+		}
 
-		HW_LOG("DMAC_CTRL Write 32bit %x", value);
+		icase(D8_CHCR) // dma8 - fromSPR
+		{
+			DMA_LOG("SPR0dma EXECUTE (fromSPR), value=0x%x", value);
+			DmaExec(dmaSPR0, mem, value);
+			return false;
+		}
 
-		psHu32(mem) = value;
-		//Check for DMAS that were started while the DMAC was disabled
-		if (((oldvalue & 0x1) == 0) && ((value & 0x1) == 1))
+		icase(D9_CHCR) // dma9 - toSPR
 		{
-			if (!QueuedDMA.empty()) StartQueuedDMA();
+			DMA_LOG("SPR1dma EXECUTE (toSPR), value=0x%x", value);
+			DmaExec(dmaSPR1, mem, value);
+			return false;
 		}
-		if ((oldvalue & 0x30) != (value & 0x30))
+			
+		icase(DMAC_CTRL)
 		{
-			DevCon.Warning("32bit Stall Source Changed to %x", (value & 0x30) >> 4);
+			u32 oldvalue = psHu32(mem);
+
+			HW_LOG("DMAC_CTRL Write 32bit %x", value);
+
+			psHu32(mem) = value;
+			//Check for DMAS that were started while the DMAC was disabled
+			if (((oldvalue & 0x1) == 0) && ((value & 0x1) == 1))
+			{
+				if (!QueuedDMA.empty()) StartQueuedDMA();
+			}
+			if ((oldvalue & 0x30) != (value & 0x30))
+			{
+				DevCon.Warning("32bit Stall Source Changed to %x", (value & 0x30) >> 4);
+			}
+			if ((oldvalue & 0xC0) != (value & 0xC0))
+			{
+				DevCon.Warning("32bit Stall Destination Changed to %x", (value & 0xC0) >> 4);
+			}
+			return false;
 		}
-		if ((oldvalue & 0xC0) != (value & 0xC0))
+
+		//Midway are a bunch of idiots, writing to E100 (reserved) instead of E010
+		//Which causes a CPCOND0 to fail.
+		icase(DMAC_FAKESTAT)
 		{
-			DevCon.Warning("32bit Stall Destination Changed to %x", (value & 0xC0) >> 4);
+			DevCon.Warning("Midway fixup addr=%x writing %x for DMA_STAT", mem, value);
+			HW_LOG("Midways own DMAC_STAT Write 32bit %x", value);
+
+			// lower 16 bits: clear on 1
+			// upper 16 bits: reverse on 1
+
+			psHu16(0xe010) &= ~(value & 0xffff);
+			psHu16(0xe012) ^= (u16)(value >> 16);
+
+			cpuTestDMACInts();
+			return false;
 		}
-		return false;
-	}
+		icase(DMAC_STAT)
+		{
+			HW_LOG("DMAC_STAT Write 32bit %x", value);
 
-	icase(DMAC_STAT)
-	{
-		HW_LOG("DMAC_STAT Write 32bit %x", value);
+			// lower 16 bits: clear on 1
+			// upper 16 bits: reverse on 1
 
-		// lower 16 bits: clear on 1
-		// upper 16 bits: reverse on 1
+			psHu16(0xe010) &= ~(value & 0xffff);
+			psHu16(0xe012) ^= (u16)(value >> 16);
 
-		psHu16(0xe010) &= ~(value & 0xffff);
-		psHu16(0xe012) ^= (u16)(value >> 16);
+			cpuTestDMACInts();
+			return false;
+		}
 
-		cpuTestDMACInts();
-		return false;
+		icase(DMAC_ENABLEW)
+		{
+			HW_LOG("DMAC_ENABLEW Write 32bit %lx", value);
+			oldvalue = psHu8(DMAC_ENABLEW + 2);
+			psHu32(DMAC_ENABLEW) = value;
+			psHu32(DMAC_ENABLER) = value;
+			if (((oldvalue & 0x1) == 1) && (((value >> 16) & 0x1) == 0))
+			{
+				if (!QueuedDMA.empty()) StartQueuedDMA();
+			}
+			return false;
+		}
 	}
 
-	icase(DMAC_ENABLEW)
-	{
-		HW_LOG("DMAC_ENABLEW Write 32bit %lx", value);
-		oldvalue = psHu8(DMAC_ENABLEW + 2);
-		psHu32(DMAC_ENABLEW) = value;
-		psHu32(DMAC_ENABLER) = value;
-		if (((oldvalue & 0x1) == 1) && (((value >> 16) & 0x1) == 0))
+	//DMA Writes are invalid to everything except the STR on CHCR when it is busy
+	if((mem & 0xf0))
+	{	
+		if((psHu32(mem & ~0xff) & 0x100) && dmacRegs.ctrl.DMAE && !psHu8(DMAC_ENABLER+2)) 
 		{
-			if (!QueuedDMA.empty()) StartQueuedDMA();
+			DevCon.Warning("Write to DMA addr %x while STR is busy! Ignoring", mem);
+			return false;
 		}
-		return false;
-	}
 	}
 
 	// fall-through: use the default writeback provided by caller.

 

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