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/* PCSX2 - PS2 Emulator for PCs |
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* Copyright (C) 2002-2010 PCSX2 Dev Team |
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* |
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* PCSX2 is free software: you can redistribute it and/or modify it under the terms |
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* of the GNU Lesser General Public License as published by the Free Software Found- |
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* ation, either version 3 of the License, or (at your option) any later version. |
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* |
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* PCSX2 is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; |
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* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR |
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* PURPOSE. See the GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License along with PCSX2. |
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* If not, see <http://www.gnu.org/licenses/>. |
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*/ |
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|
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|
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#include "PrecompiledHeader.h" |
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#include "Common.h" |
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#include "Hardware.h" |
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|
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#include "IPU/IPUdma.h" |
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#include "ps2/HwInternal.h" |
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|
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bool DMACh::transfer(const char *s, tDMA_TAG* ptag) |
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{ |
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if (ptag == NULL) // Is ptag empty? |
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{ |
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throwBusError(s); |
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return false; |
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} |
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chcrTransfer(ptag); |
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|
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qwcTransfer(ptag); |
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return true; |
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} |
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|
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void DMACh::unsafeTransfer(tDMA_TAG* ptag) |
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{ |
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chcrTransfer(ptag); |
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qwcTransfer(ptag); |
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} |
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|
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tDMA_TAG *DMACh::getAddr(u32 addr, u32 num, bool write) |
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{ |
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tDMA_TAG *ptr = dmaGetAddr(addr, write); |
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if (ptr == NULL) |
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{ |
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throwBusError("dmaGetAddr"); |
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setDmacStat(num); |
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chcr.STR = false; |
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} |
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|
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return ptr; |
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} |
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|
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tDMA_TAG *DMACh::DMAtransfer(u32 addr, u32 num) |
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{ |
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tDMA_TAG *tag = getAddr(addr, num, false); |
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|
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if (tag == NULL) return NULL; |
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|
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chcrTransfer(tag); |
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qwcTransfer(tag); |
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return tag; |
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} |
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|
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tDMA_TAG DMACh::dma_tag() |
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{ |
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return chcr.tag(); |
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} |
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|
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wxString DMACh::cmq_to_str() const |
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{ |
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return wxsFormat(L"chcr = %lx, madr = %lx, qwc = %lx", chcr._u32, madr, qwc); |
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} |
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|
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wxString DMACh::cmqt_to_str() const |
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{ |
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return wxsFormat(L"chcr = %lx, madr = %lx, qwc = %lx, tadr = %1x", chcr._u32, madr, qwc, tadr); |
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} |
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|
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__fi void throwBusError(const char *s) |
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{ |
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Console.Error("%s BUSERR", s); |
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dmacRegs.stat.BEIS = true; |
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} |
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|
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__fi void setDmacStat(u32 num) |
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{ |
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dmacRegs.stat.set_flags(1 << num); |
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} |
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|
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// Note: Dma addresses are guaranteed to be aligned to 16 bytes (128 bits) |
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__fi tDMA_TAG *SPRdmaGetAddr(u32 addr, bool write) |
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{ |
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// if (addr & 0xf) { DMA_LOG("*PCSX2*: DMA address not 128bit aligned: %8.8x", addr); } |
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|
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//For some reason Getaway references SPR Memory from itself using SPR0, oh well, let it i guess... |
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if((addr & 0x70000000) == 0x70000000) |
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{ |
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return (tDMA_TAG*)&eeMem->Scratch[addr & 0x3ff0]; |
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} |
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|
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// FIXME: Why??? DMA uses physical addresses |
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addr &= 0x1ffffff0; |
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|
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if (addr < Ps2MemSize::Base) |
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{ |
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return (tDMA_TAG*)&eeMem->Main[addr]; |
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} |
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else if (addr < 0x10000000) |
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{ |
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return (tDMA_TAG*)(write ? eeMem->ZeroWrite : eeMem->ZeroRead); |
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} |
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else if ((addr >= 0x11004000) && (addr < 0x11010000)) |
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{ |
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//Access for VU Memory |
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return (tDMA_TAG*)vtlb_GetPhyPtr(addr & 0x1FFFFFF0); |
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} |
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else |
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{ |
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Console.Error( "*PCSX2*: DMA error: %8.8x", addr); |
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return NULL; |
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} |
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} |
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|
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// Note: Dma addresses are guaranteed to be aligned to 16 bytes (128 bits) |
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__ri tDMA_TAG *dmaGetAddr(u32 addr, bool write) |
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{ |
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// if (addr & 0xf) { DMA_LOG("*PCSX2*: DMA address not 128bit aligned: %8.8x", addr); } |
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if (DMA_TAG(addr).SPR) return (tDMA_TAG*)&eeMem->Scratch[addr & 0x3ff0]; |
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|
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// FIXME: Why??? DMA uses physical addresses |
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addr &= 0x1ffffff0; |
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|
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if (addr < Ps2MemSize::Base) |
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{ |
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return (tDMA_TAG*)&eeMem->Main[addr]; |
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} |
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else if (addr < 0x10000000) |
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{ |
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return (tDMA_TAG*)(write ? eeMem->ZeroWrite : eeMem->ZeroRead); |
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} |
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else if (addr < 0x10004000) |
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{ |
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// Secret scratchpad address for DMA = end of maximum main memory? |
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//Console.Warning("Writing to the scratchpad without the SPR flag set!"); |
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return (tDMA_TAG*)&eeMem->Scratch[addr & 0x3ff0]; |
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} |
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else |
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{ |
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Console.Error( "*PCSX2*: DMA error: %8.8x", addr); |
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return NULL; |
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} |
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} |
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|
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|
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// Returns true if the DMA is enabled and executed successfully. Returns false if execution |
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// was blocked (DMAE or master DMA enabler). |
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static bool QuickDmaExec( void (*func)(), u32 mem) |
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{ |
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bool ret = false; |
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DMACh& reg = (DMACh&)psHu32(mem); |
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|
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if (reg.chcr.STR && dmacRegs.ctrl.DMAE && !psHu8(DMAC_ENABLER+2)) |
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{ |
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func(); |
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ret = true; |
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} |
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|
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return ret; |
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} |
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|
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|
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static tDMAC_QUEUE QueuedDMA(0); |
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static u32 oldvalue = 0; |
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|
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static void StartQueuedDMA() |
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{ |
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if (QueuedDMA.VIF0) { DMA_LOG("Resuming DMA for VIF0"); QueuedDMA.VIF0 = !QuickDmaExec(dmaVIF0, D0_CHCR); } |
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if (QueuedDMA.VIF1) { DMA_LOG("Resuming DMA for VIF1"); QueuedDMA.VIF1 = !QuickDmaExec(dmaVIF1, D1_CHCR); } |
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if (QueuedDMA.GIF ) { DMA_LOG("Resuming DMA for GIF" ); QueuedDMA.GIF = !QuickDmaExec(dmaGIF , D2_CHCR); } |
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if (QueuedDMA.IPU0) { DMA_LOG("Resuming DMA for IPU0"); QueuedDMA.IPU0 = !QuickDmaExec(dmaIPU0, D3_CHCR); } |
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if (QueuedDMA.IPU1) { DMA_LOG("Resuming DMA for IPU1"); QueuedDMA.IPU1 = !QuickDmaExec(dmaIPU1, D4_CHCR); } |
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if (QueuedDMA.SIF0) { DMA_LOG("Resuming DMA for SIF0"); QueuedDMA.SIF0 = !QuickDmaExec(dmaSIF0, D5_CHCR); } |
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if (QueuedDMA.SIF1) { DMA_LOG("Resuming DMA for SIF1"); QueuedDMA.SIF1 = !QuickDmaExec(dmaSIF1, D6_CHCR); } |
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if (QueuedDMA.SIF2) { DMA_LOG("Resuming DMA for SIF2"); QueuedDMA.SIF2 = !QuickDmaExec(dmaSIF2, D7_CHCR); } |
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if (QueuedDMA.SPR0) { DMA_LOG("Resuming DMA for SPR0"); QueuedDMA.SPR0 = !QuickDmaExec(dmaSPR0, D8_CHCR); } |
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if (QueuedDMA.SPR1) { DMA_LOG("Resuming DMA for SPR1"); QueuedDMA.SPR1 = !QuickDmaExec(dmaSPR1, D9_CHCR); } |
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} |
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|
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static __ri void DmaExec( void (*func)(), u32 mem, u32 value ) |
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{ |
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DMACh& reg = (DMACh&)psHu32(mem); |
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tDMA_CHCR chcr(value); |
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|
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//It's invalid for the hardware to write a DMA while it is active, not without Suspending the DMAC |
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if (reg.chcr.STR) |
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{ |
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const uint channel = ChannelNumber(mem); |
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|
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if(psHu8(DMAC_ENABLER+2) == 1) //DMA is suspended so we can allow writes to anything |
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{ |
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//If it stops the DMA, we need to clear any pending interrupts so the DMA doesnt continue. |
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if(chcr.STR == 0) |
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{ |
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//DevCon.Warning(L"32bit %s DMA Stopped on Suspend", ChcrName(mem)); |
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if(channel == 1) |
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{ |
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cpuClearInt( 10 ); |
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QueuedDMA._u16 &= ~(1 << 10); //Clear any queued DMA requests for this channel |
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} |
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else if(channel == 2) |
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{ |
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cpuClearInt( 11 ); |
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QueuedDMA._u16 &= ~(1 << 11); //Clear any queued DMA requests for this channel |
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} |
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|
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cpuClearInt( channel ); |
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QueuedDMA._u16 &= ~(1 << channel); //Clear any queued DMA requests for this channel |
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} |
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//Sanity Check for possible future bug fix0rs ;p |
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//Spams on Persona 4 opening. |
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//if(reg.chcr.TAG != chcr.TAG) DevCon.Warning(L"32bit CHCR Tag on %s changed to %x from %x QWC = %x Channel Active", ChcrName(mem), chcr.TAG, reg.chcr.TAG, reg.qwc); |
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//Here we update the LOWER CHCR, if a chain is stopped half way through, it can be manipulated in to a different mode |
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//But we need to preserve the existing tag for now |
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reg.chcr.set((reg.chcr.TAG << 16) | chcr.lower()); |
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return; |
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} |
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else //Else the DMA is running (Not Suspended), so we cant touch it! |
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{ |
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//As the manual states "Fields other than STR can only be written to when the DMA is stopped" |
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//Also "The DMA may not stop properly just by writing 0 to STR" |
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//So the presumption is that STR can be written to (ala force stop the DMA) but nothing else |
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|
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if(chcr.STR == 0) |
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{ |
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//DevCon.Warning(L"32bit Force Stopping %s (Current CHCR %x) while DMA active", ChcrName(mem), reg.chcr._u32, chcr._u32); |
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reg.chcr.STR = 0; |
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//We need to clear any existing DMA loops that are in progress else they will continue! |
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|
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if(channel == 1) |
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{ |
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cpuClearInt( 10 ); |
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QueuedDMA._u16 &= ~(1 << 10); //Clear any queued DMA requests for this channel |
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} |
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else if(channel == 2) |
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{ |
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cpuClearInt( 11 ); |
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QueuedDMA._u16 &= ~(1 << 11); //Clear any queued DMA requests for this channel |
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} |
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|
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cpuClearInt( channel ); |
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QueuedDMA._u16 &= ~(1 << channel); //Clear any queued DMA requests for this channel |
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} |
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//else DevCon.Warning(L"32bit Attempted to change %s CHCR (Currently %x) with %x while DMA active, ignoring QWC = %x", ChcrName(mem), reg.chcr._u32, chcr._u32, reg.qwc); |
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return; |
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} |
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|
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} |
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|
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//if(reg.chcr.TAG != chcr.TAG && chcr.MOD == CHAIN_MODE) DevCon.Warning(L"32bit CHCR Tag on %s changed to %x from %x QWC = %x Channel Not Active", ChcrName(mem), chcr.TAG, reg.chcr.TAG, reg.qwc); |
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|
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reg.chcr.set(value); |
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|
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if (reg.chcr.STR && dmacRegs.ctrl.DMAE && !psHu8(DMAC_ENABLER+2)) |
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{ |
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func(); |
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} |
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else if(reg.chcr.STR) |
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{ |
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//DevCon.Warning(L"32bit %s DMA Start while DMAC Disabled\n", ChcrName(mem)); |
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QueuedDMA._u16 |= (1 << ChannelNumber(mem)); //Queue the DMA up to be started then the DMA's are Enabled and or the Suspend is lifted |
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} //else QueuedDMA._u16 &~= (1 << ChannelNumber(mem)); // |
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} |
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|
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template< uint page > |
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__fi u32 dmacRead32( u32 mem ) |
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{ |
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// Fixme: OPH hack. Toggle the flag on each GIF_STAT access. (rama) |
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if (IsPageFor(mem) && (mem == GIF_STAT) && CHECK_OPHFLAGHACK) |
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{ |
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gifRegs.stat.OPH = !gifRegs.stat.OPH; |
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} |
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|
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return psHu32(mem); |
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} |
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|
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// Returns TRUE if the caller should do writeback of the register to eeHw; false if the |
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// register has no writeback, or if the writeback is handled internally. |
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template< uint page > |
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__fi bool dmacWrite32( u32 mem, mem32_t& value ) |
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{ |
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iswitch(mem) { |
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icase(D0_CHCR) // dma0 - vif0 |
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{ |
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DMA_LOG("VIF0dma EXECUTE, value=0x%x", value); |
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DmaExec(dmaVIF0, mem, value); |
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return false; |
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} |
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|
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icase(D1_CHCR) // dma1 - vif1 - chcr |
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{ |
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DMA_LOG("VIF1dma EXECUTE, value=0x%x", value); |
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DmaExec(dmaVIF1, mem, value); |
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return false; |
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} |
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|
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icase(D2_CHCR) // dma2 - gif |
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{ |
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DMA_LOG("GIFdma EXECUTE, value=0x%x", value); |
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DmaExec(dmaGIF, mem, value); |
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return false; |
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} |
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|
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icase(D3_CHCR) // dma3 - fromIPU |
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{ |
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DMA_LOG("IPU0dma EXECUTE, value=0x%x\n", value); |
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DmaExec(dmaIPU0, mem, value); |
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return false; |
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} |
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|
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icase(D4_CHCR) // dma4 - toIPU |
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{ |
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DMA_LOG("IPU1dma EXECUTE, value=0x%x\n", value); |
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DmaExec(dmaIPU1, mem, value); |
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return false; |
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} |
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|
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icase(D5_CHCR) // dma5 - sif0 |
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{ |
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DMA_LOG("SIF0dma EXECUTE, value=0x%x", value); |
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DmaExec(dmaSIF0, mem, value); |
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return false; |
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} |
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|
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icase(D6_CHCR) // dma6 - sif1 |
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{ |
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DMA_LOG("SIF1dma EXECUTE, value=0x%x", value); |
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DmaExec(dmaSIF1, mem, value); |
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return false; |
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} |
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|
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icase(D7_CHCR) // dma7 - sif2 |
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{ |
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DMA_LOG("SIF2dma EXECUTE, value=0x%x", value); |
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DmaExec(dmaSIF2, mem, value); |
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return false; |
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} |
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|
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icase(D8_CHCR) // dma8 - fromSPR |
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{ |
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DMA_LOG("SPR0dma EXECUTE (fromSPR), value=0x%x", value); |
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DmaExec(dmaSPR0, mem, value); |
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return false; |
| 356 |
} |
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|
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icase(D9_CHCR) // dma9 - toSPR |
| 359 |
{ |
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DMA_LOG("SPR1dma EXECUTE (toSPR), value=0x%x", value); |
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DmaExec(dmaSPR1, mem, value); |
| 362 |
return false; |
| 363 |
} |
| 364 |
|
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icase(DMAC_CTRL) |
| 366 |
{ |
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u32 oldvalue = psHu32(mem); |
| 368 |
|
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HW_LOG("DMAC_CTRL Write 32bit %x", value); |
| 370 |
|
| 371 |
psHu32(mem) = value; |
| 372 |
//Check for DMAS that were started while the DMAC was disabled |
| 373 |
if (((oldvalue & 0x1) == 0) && ((value & 0x1) == 1)) |
| 374 |
{ |
| 375 |
if (!QueuedDMA.empty()) StartQueuedDMA(); |
| 376 |
} |
| 377 |
if ((oldvalue & 0x30) != (value & 0x30)) |
| 378 |
{ |
| 379 |
DevCon.Warning("32bit Stall Source Changed to %x", (value & 0x30) >> 4); |
| 380 |
} |
| 381 |
if ((oldvalue & 0xC0) != (value & 0xC0)) |
| 382 |
{ |
| 383 |
DevCon.Warning("32bit Stall Destination Changed to %x", (value & 0xC0) >> 4); |
| 384 |
} |
| 385 |
return false; |
| 386 |
} |
| 387 |
|
| 388 |
icase(DMAC_STAT) |
| 389 |
{ |
| 390 |
HW_LOG("DMAC_STAT Write 32bit %x", value); |
| 391 |
|
| 392 |
// lower 16 bits: clear on 1 |
| 393 |
// upper 16 bits: reverse on 1 |
| 394 |
|
| 395 |
psHu16(0xe010) &= ~(value & 0xffff); |
| 396 |
psHu16(0xe012) ^= (u16)(value >> 16); |
| 397 |
|
| 398 |
cpuTestDMACInts(); |
| 399 |
return false; |
| 400 |
} |
| 401 |
|
| 402 |
icase(DMAC_ENABLEW) |
| 403 |
{ |
| 404 |
HW_LOG("DMAC_ENABLEW Write 32bit %lx", value); |
| 405 |
oldvalue = psHu8(DMAC_ENABLEW + 2); |
| 406 |
psHu32(DMAC_ENABLEW) = value; |
| 407 |
psHu32(DMAC_ENABLER) = value; |
| 408 |
if (((oldvalue & 0x1) == 1) && (((value >> 16) & 0x1) == 0)) |
| 409 |
{ |
| 410 |
if (!QueuedDMA.empty()) StartQueuedDMA(); |
| 411 |
} |
| 412 |
return false; |
| 413 |
} |
| 414 |
} |
| 415 |
|
| 416 |
// fall-through: use the default writeback provided by caller. |
| 417 |
return true; |
| 418 |
} |
| 419 |
|
| 420 |
template u32 dmacRead32<0x03>( u32 mem ); |
| 421 |
|
| 422 |
template bool dmacWrite32<0x00>( u32 mem, mem32_t& value ); |
| 423 |
template bool dmacWrite32<0x01>( u32 mem, mem32_t& value ); |
| 424 |
template bool dmacWrite32<0x02>( u32 mem, mem32_t& value ); |
| 425 |
template bool dmacWrite32<0x03>( u32 mem, mem32_t& value ); |
| 426 |
template bool dmacWrite32<0x04>( u32 mem, mem32_t& value ); |
| 427 |
template bool dmacWrite32<0x05>( u32 mem, mem32_t& value ); |
| 428 |
template bool dmacWrite32<0x06>( u32 mem, mem32_t& value ); |
| 429 |
template bool dmacWrite32<0x07>( u32 mem, mem32_t& value ); |
| 430 |
template bool dmacWrite32<0x08>( u32 mem, mem32_t& value ); |
| 431 |
template bool dmacWrite32<0x09>( u32 mem, mem32_t& value ); |
| 432 |
template bool dmacWrite32<0x0a>( u32 mem, mem32_t& value ); |
| 433 |
template bool dmacWrite32<0x0b>( u32 mem, mem32_t& value ); |
| 434 |
template bool dmacWrite32<0x0c>( u32 mem, mem32_t& value ); |
| 435 |
template bool dmacWrite32<0x0d>( u32 mem, mem32_t& value ); |
| 436 |
template bool dmacWrite32<0x0e>( u32 mem, mem32_t& value ); |
| 437 |
template bool dmacWrite32<0x0f>( u32 mem, mem32_t& value ); |
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