/[pcsx2_0.9.7]/trunk/pcsx2/Vif_Codes.cpp
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Annotation of /trunk/pcsx2/Vif_Codes.cpp

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Revision 62 - (hide annotations) (download)
Tue Sep 7 11:08:22 2010 UTC (9 years, 10 months ago) by william
File size: 20074 byte(s)
Auto Commited Import of: pcsx2-0.9.7-r3738-debug in ./trunk
1 william 31 /* PCSX2 - PS2 Emulator for PCs
2     * Copyright (C) 2002-2010 PCSX2 Dev Team
3     *
4     * PCSX2 is free software: you can redistribute it and/or modify it under the terms
5     * of the GNU Lesser General Public License as published by the Free Software Found-
6     * ation, either version 3 of the License, or (at your option) any later version.
7     *
8     * PCSX2 is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
9     * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
10     * PURPOSE. See the GNU General Public License for more details.
11     *
12     * You should have received a copy of the GNU General Public License along with PCSX2.
13     * If not, see <http://www.gnu.org/licenses/>.
14     */
15    
16     #include "PrecompiledHeader.h"
17     #include "Common.h"
18     #include "GS.h"
19     #include "Gif.h"
20     #include "Vif_Dma.h"
21     #include "newVif.h"
22     #include "VUmicro.h"
23    
24 william 62 #define vifOp(vifCodeName) _vifT int __fastcall vifCodeName(int pass, const u32 *data)
25 william 31 #define pass1 if (pass == 0)
26     #define pass2 if (pass == 1)
27     #define pass3 if (pass == 2)
28     #define vif1Only() { if (!idx) return vifCode_Null<idx>(pass, (u32*)data); }
29     vifOp(vifCode_Null);
30    
31     //------------------------------------------------------------------
32     // Vif0/Vif1 Misc Functions
33     //------------------------------------------------------------------
34    
35 william 62 static __fi void vifFlush(int idx) {
36 william 31 if (!idx) vif0FLUSH();
37     else vif1FLUSH();
38     }
39    
40 william 62 static __fi void vuExecMicro(int idx, u32 addr) {
41 william 31 VURegs* VU = nVif[idx].VU;
42 william 62 VIFregisters& vifRegs = VU->GetVifRegs();
43     int startcycles = 0;
44     //vifFlush(idx);
45 william 31
46 william 62 //if(vifX.vifstalled == true) return;
47    
48     if (vifRegs.itops > (idx ? 0x3ffu : 0xffu)) {
49     Console.WriteLn("VIF%d ITOP overrun! %x", idx, vifRegs.itops);
50     vifRegs.itops &= (idx ? 0x3ffu : 0xffu);
51 william 31 }
52    
53 william 62 vifRegs.itop = vifRegs.itops;
54 william 31
55     if (idx) {
56     // in case we're handling a VIF1 execMicro, set the top with the tops value
57 william 62 vifRegs.top = vifRegs.tops & 0x3ff;
58 william 31
59     // is DBF flag set in VIF_STAT?
60 william 62 if (vifRegs.stat.DBF) {
61 william 31 // it is, so set tops with base, and clear the stat DBF flag
62 william 62 vifRegs.tops = vifRegs.base;
63     vifRegs.stat.DBF = false;
64 william 31 }
65     else {
66     // it is not, so set tops with base + offset, and set stat DBF flag
67 william 62 vifRegs.tops = vifRegs.base + vifRegs.ofst;
68     vifRegs.stat.DBF = true;
69 william 31 }
70     }
71    
72 william 62 if(!idx)startcycles = VU0.cycle;
73     else startcycles = VU1.cycle;
74    
75 william 31 if (!idx) vu0ExecMicro(addr);
76     else vu1ExecMicro(addr);
77 william 62
78     if(!idx) { g_vu0Cycles += (VU0.cycle-startcycles) * BIAS; g_packetsizeonvu = vif0.vifpacketsize; }
79     else { g_vu1Cycles += (VU1.cycle-startcycles) * BIAS; g_packetsizeonvu = vif1.vifpacketsize; }
80     //DevCon.Warning("Ran VU%x, VU0 Cycles %x, VU1 Cycles %x", idx, g_vu0Cycles, g_vu1Cycles);
81     GetVifX.vifstalled = true;
82 william 31 }
83    
84     u8 schedulepath3msk = 0;
85    
86     void Vif1MskPath3() {
87    
88 william 62 vif1Regs.mskpath3 = schedulepath3msk & 0x1;
89     GIF_LOG("VIF MSKPATH3 %x gif str %x path3 status %x", vif1Regs.mskpath3, gifch.chcr.STR, GSTransferStatus.PTH3);
90     gifRegs.stat.M3P = vif1Regs.mskpath3;
91    
92     if (!vif1Regs.mskpath3)
93     {
94     //if(GSTransferStatus.PTH3 > TRANSFER_MODE && gif->chcr.STR) GSTransferStatus.PTH3 = TRANSFER_MODE;
95     //DevCon.Warning("Mask off");
96     //if(GSTransferStatus.PTH3 >= PENDINGSTOP_MODE) GSTransferStatus.PTH3 = IDLE_MODE;
97     if(gifRegs.stat.P3Q)
98 william 31 {
99 william 62 gsInterrupt();//gsInterrupt();
100 william 31 }
101 william 62
102     }// else if(!gif->chcr.STR && GSTransferStatus.PTH3 == IDLE_MODE) GSTransferStatus.PTH3 = STOPPED_MODE;//else DevCon.Warning("Mask on");
103 william 31
104     schedulepath3msk = 0;
105     }
106    
107     //------------------------------------------------------------------
108     // Vif0/Vif1 Code Implementations
109     //------------------------------------------------------------------
110    
111     vifOp(vifCode_Base) {
112     vif1Only();
113 william 62 pass1 { vif1Regs.base = vif1Regs.code & 0x3ff; vif1.cmd = 0; }
114     pass3 { VifCodeLog("Base"); }
115 william 31 return 0;
116     }
117    
118 william 62 extern bool SIGNAL_IMR_Pending;
119    
120     template<int idx> __fi int _vifCode_Direct(int pass, const u8* data, bool isDirectHL) {
121 william 31 pass1 {
122     vif1Only();
123 william 62 int vifImm = (u16)vif1Regs.code;
124 william 31 vif1.tag.size = vifImm ? (vifImm*4) : (65536*4);
125 william 62 vif1.vifstalled = true;
126     gifRegs.stat.P2Q = true;
127     if (gifRegs.stat.PSE) // temporarily stop
128     {
129     Console.WriteLn("Gif dma temp paused? VIF DIRECT");
130     vif1.GifWaitState = 3;
131     vif1Regs.stat.VGW = true;
132     }
133     //Should cause this to split here to try and time PATH3 right.
134     return 0;
135 william 31 }
136     pass2 {
137     vif1Only();
138 william 62
139     if (GSTransferStatus.PTH3 < IDLE_MODE || gifRegs.stat.P1Q == true)
140 william 31 {
141 william 62 if(gifRegs.stat.APATH == GIF_APATH2 || ((GSTransferStatus.PTH3 <= IMAGE_MODE && gifRegs.stat.IMT && (vif1.cmd & 0x7f) == 0x50)) && gifRegs.stat.P1Q == false)
142     {
143     //Do nothing, allow it
144     vif1Regs.stat.VGW = false;
145     //if(gifRegs.stat.APATH != GIF_APATH2)DevCon.Warning("Continue DIRECT/HL %x P3 %x APATH %x P1Q %x", vif1.cmd, GSTransferStatus.PTH3, gifRegs.stat.APATH, gifRegs.stat.P1Q);
146     }
147     else
148     {
149     //DevCon.Warning("Stall DIRECT/HL %x P3 %x APATH %x P1Q %x", vif1.cmd, GSTransferStatus.PTH3, gifRegs.stat.APATH, gifRegs.stat.P1Q);
150     vif1Regs.stat.VGW = true; // PATH3 is in image mode (DIRECTHL), or busy (BOTH no IMT)
151     vif1.GifWaitState = 0;
152     vif1.vifstalled = true;
153     return 0;
154     }
155     }
156     if(SIGNAL_IMR_Pending == true)
157     {
158     DevCon.Warning("Path 2 Paused (At start)");
159 william 31 vif1.vifstalled = true;
160     return 0;
161     }
162 william 62 if (gifRegs.stat.PSE) // temporarily stop
163     {
164     Console.WriteLn("Gif dma temp paused? VIF DIRECT");
165     vif1.GifWaitState = 3;
166     vif1.vifstalled = true;
167     vif1Regs.stat.VGW = true;
168     return 0;
169     }
170 william 31
171 william 62 // HACK ATTACK!
172     // we shouldn't be clearing the queue flag here at all. Ideally, the queue statuses
173     // should be checked, handled, and cleared from the EOP check in GIFPath only. --air
174     gifRegs.stat.clear_flags(GIF_STAT_P2Q);
175 william 31
176 william 62 uint minSize = aMin(vif1.vifpacketsize, vif1.tag.size);
177     uint ret;
178 william 31
179 william 62 if(minSize < 4)
180     {
181     // When TTE==1, the VIF might end up sending us 8-byte packets instead of the usual 16-byte
182     // variety, if DIRECT tags cross chain dma boundaries. The actual behavior of real hardware
183     // is unknown at this time, but it seems that games *only* ever try to upload zero'd data
184     // in this situation.
185     //
186     // Games that use TTE==1 and DIRECT in this fashion: ICO
187     //
188     // Because DIRECT normally has a strict QWC alignment requirement, and this funky behavior
189     // only seems to happen on TTE mode transfers with their split-64-bit packets, there shouldn't
190     // be any need to worry about queuing more than 16 bytes of data,
191     //
192    
193     static __aligned16 u32 partial_write[4];
194     static uint partial_count = 0;
195    
196     for( uint i=0; i<(minSize & 3); ++i)
197     partial_write[partial_count++] = ((u32*)data)[i];
198    
199     pxAssume( partial_count <= 4 );
200     ret = 0;
201     if (partial_count == 4)
202     {
203     GetMTGS().PrepDataPacket(GIF_PATH_2, 1);
204     GIFPath_CopyTag(GIF_PATH_2, (u128*)partial_write, 1);
205     GetMTGS().SendDataPacket();
206     partial_count = 0;
207     ret = 4;
208 william 31 }
209 william 62 }
210     else
211     {
212     if (!minSize)
213     DevCon.Warning("VIF DIRECT (PATH2): No Data Transfer?");
214    
215     // TTE=1 mode is the only time we should be getting DIRECT packet sizes that are
216     // not a multiple of QWC, and those are assured to be under 128 bits in size.
217     // So if this assert is triggered then it probably means something else is amiss.
218     pxAssertMsg((minSize & 3) == 0, "DIRECT packet size is not a multiple of QWC." );
219    
220     GetMTGS().PrepDataPacket(GIF_PATH_2, minSize/4);
221     ret = GIFPath_CopyTag(GIF_PATH_2, (u128*)data, minSize/4)*4;
222 william 31 GetMTGS().SendDataPacket();
223 william 62 }
224    
225     vif1.tag.size -= ret;
226    
227     if(vif1.tag.size == 0)
228     {
229 william 31 vif1.cmd = 0;
230     }
231 william 62 vif1.vifstalled = true;
232 william 31 return ret;
233     }
234     return 0;
235     }
236    
237     vifOp(vifCode_Direct) {
238 william 62 pass3 { VifCodeLog("Direct"); }
239 william 31 return _vifCode_Direct<idx>(pass, (u8*)data, 0);
240     }
241    
242     vifOp(vifCode_DirectHL) {
243 william 62 pass3 { VifCodeLog("DirectHL"); }
244 william 31 return _vifCode_Direct<idx>(pass, (u8*)data, 1);
245     }
246    
247     // ToDo: FixMe
248     vifOp(vifCode_Flush) {
249     vif1Only();
250 william 62 vifStruct& vifX = GetVifX;
251     pass1 { vifFlush(idx); vifX.cmd = 0; }
252     pass3 { VifCodeLog("Flush"); }
253 william 31 return 0;
254     }
255    
256     // ToDo: FixMe
257     vifOp(vifCode_FlushA) {
258     vif1Only();
259 william 62 vifStruct& vifX = GetVifX;
260 william 31 pass1 {
261 william 62 vifFlush(idx);
262 william 31 // Gif is already transferring so wait for it.
263 william 62 if (gifRegs.stat.P1Q || GSTransferStatus.PTH3 <= PENDINGSTOP_MODE) {
264     //DevCon.Warning("VIF FlushA Wait MSK = %x", vif1Regs.mskpath3);
265     //
266    
267 william 31 //DevCon.WriteLn("FlushA path3 Wait! PTH3 MD %x STR %x", GSTransferStatus.PTH3, gif->chcr.STR);
268 william 62 vif1Regs.stat.VGW = true;
269     vifX.GifWaitState = 1;
270 william 31 vifX.vifstalled = true;
271 william 62 } // else DevCon.WriteLn("FlushA path3 no Wait! PTH3 MD %x STR %x", GSTransferStatus.PTH3, gif->chcr.STR);
272    
273 william 31 vifX.cmd = 0;
274     }
275 william 62 pass3 { VifCodeLog("FlushA"); }
276 william 31 return 0;
277     }
278    
279     // ToDo: FixMe
280     vifOp(vifCode_FlushE) {
281 william 62 vifStruct& vifX = GetVifX;
282 william 31 pass1 { vifFlush(idx); vifX.cmd = 0; }
283 william 62 pass3 { VifCodeLog("FlushE"); }
284 william 31 return 0;
285     }
286    
287     vifOp(vifCode_ITop) {
288 william 62 pass1 { vifXRegs.itops = vifXRegs.code & 0x3ff; GetVifX.cmd = 0; }
289     pass3 { VifCodeLog("ITop"); }
290 william 31 return 0;
291     }
292    
293     vifOp(vifCode_Mark) {
294 william 62 vifStruct& vifX = GetVifX;
295 william 31 pass1 {
296 william 62 vifXRegs.mark = (u16)vifXRegs.code;
297     vifXRegs.stat.MRK = true;
298 william 31 vifX.cmd = 0;
299     }
300 william 62 pass3 { VifCodeLog("Mark"); }
301 william 31 return 0;
302     }
303    
304 william 62 static __fi void _vifCode_MPG(int idx, u32 addr, const u32 *data, int size) {
305 william 31 VURegs& VUx = idx ? VU1 : VU0;
306     pxAssume(VUx.Micro > 0);
307    
308 william 62 if (memcmp_mmx(VUx.Micro + addr, data, size*4)) {
309     // Clear VU memory before writing!
310     // (VUs expect size to be 32-bit scale, same as VIF's internal working sizes)
311     if (!idx) CpuVU0->Clear(addr, size);
312     else CpuVU1->Clear(addr, size);
313     memcpy_fast(VUx.Micro + addr, data, size*4);
314 william 31 }
315     }
316    
317     vifOp(vifCode_MPG) {
318 william 62 vifStruct& vifX = GetVifX;
319 william 31 pass1 {
320 william 62 int vifNum = (u8)(vifXRegs.code >> 16);
321     vifX.tag.addr = (u16)(vifXRegs.code << 3) & (idx ? 0x3fff : 0xfff);
322 william 31 vifX.tag.size = vifNum ? (vifNum*2) : 512;
323 william 62 //vifFlush(idx);
324 william 31 return 1;
325     }
326     pass2 {
327     if (vifX.vifpacketsize < vifX.tag.size) { // Partial Transfer
328 william 62 if((vifX.tag.addr + vifX.vifpacketsize*4) > (idx ? 0x4000 : 0x1000)) {
329 william 31 DevCon.Warning("Vif%d MPG Split Overflow", idx);
330     }
331     _vifCode_MPG(idx, vifX.tag.addr, data, vifX.vifpacketsize);
332 william 62 vifX.tag.addr += vifX.vifpacketsize * 4;
333 william 31 vifX.tag.size -= vifX.vifpacketsize;
334     return vifX.vifpacketsize;
335     }
336     else { // Full Transfer
337 william 62 if((vifX.tag.addr + vifX.tag.size*4) > (idx ? 0x4000 : 0x1000)) {
338 william 31 DevCon.Warning("Vif%d MPG Split Overflow", idx);
339     }
340     _vifCode_MPG(idx, vifX.tag.addr, data, vifX.tag.size);
341     int ret = vifX.tag.size;
342     vifX.tag.size = 0;
343     vifX.cmd = 0;
344     return ret;
345     }
346     }
347 william 62 pass3 { VifCodeLog("MPG"); }
348 william 31 return 0;
349     }
350    
351     vifOp(vifCode_MSCAL) {
352 william 62 vifStruct& vifX = GetVifX;
353     pass1 { vifFlush(idx); vuExecMicro(idx, (u16)(vifXRegs.code) << 3); vifX.cmd = 0;}
354     pass3 { VifCodeLog("MSCAL"); }
355 william 31 return 0;
356     }
357    
358     vifOp(vifCode_MSCALF) {
359 william 62 vifStruct& vifX = GetVifX;
360     pass1 { vifFlush(idx); vuExecMicro(idx, (u16)(vifXRegs.code) << 3); vifX.cmd = 0; }
361     pass3 { VifCodeLog("MSCALF"); }
362 william 31 return 0;
363     }
364    
365     vifOp(vifCode_MSCNT) {
366 william 62 vifStruct& vifX = GetVifX;
367     pass1 { vifFlush(idx); vuExecMicro(idx, -1); vifX.cmd = 0; }
368     pass3 { VifCodeLog("MSCNT"); }
369 william 31 return 0;
370     }
371    
372     // ToDo: FixMe
373     vifOp(vifCode_MskPath3) {
374     vif1Only();
375     pass1 {
376 william 62 if (vif1ch.chcr.STR && vif1.lastcmd != 0x13) {
377     schedulepath3msk = 0x10 | ((vif1Regs.code >> 15) & 0x1);
378 william 31 vif1.vifstalled = true;
379     }
380     else {
381 william 62 schedulepath3msk = (vif1Regs.code >> 15) & 0x1;
382 william 31 Vif1MskPath3();
383     }
384 william 62 vif1.cmd = 0;
385 william 31 }
386 william 62 pass3 { VifCodeLog("MskPath3"); }
387 william 31 return 0;
388     }
389    
390     vifOp(vifCode_Nop) {
391 william 62 pass1 { GetVifX.cmd = 0; }
392     pass3 { VifCodeLog("Nop"); }
393 william 31 return 0;
394     }
395    
396     // ToDo: Review Flags
397     vifOp(vifCode_Null) {
398 william 62 vifStruct& vifX = GetVifX;
399 william 31 pass1 {
400     // if ME1, then force the vif to interrupt
401 william 62 if (!(vifXRegs.err.ME1)) { // Ignore vifcode and tag mismatch error
402 william 31 Console.WriteLn("Vif%d: Unknown VifCmd! [%x]", idx, vifX.cmd);
403 william 62 vifXRegs.stat.ER1 = true;
404     vifX.vifstalled = true;
405 william 31 //vifX.irq++;
406     }
407     vifX.cmd = 0;
408     }
409     pass2 { Console.Error("Vif%d bad vifcode! [CMD = %x]", idx, vifX.cmd); }
410 william 62 pass3 { VifCodeLog("Null"); }
411 william 31 return 0;
412     }
413    
414     vifOp(vifCode_Offset) {
415     vif1Only();
416     pass1 {
417 william 62 vif1Regs.stat.DBF = false;
418     vif1Regs.ofst = vif1Regs.code & 0x3ff;
419     vif1Regs.tops = vif1Regs.base;
420     vif1.cmd = 0;
421 william 31 }
422 william 62 pass3 { VifCodeLog("Offset"); }
423 william 31 return 0;
424     }
425    
426 william 62 template<int idx> static __fi int _vifCode_STColRow(const u32* data, u32* pmem1, u32* pmem2) {
427     vifStruct& vifX = GetVifX;
428    
429     int ret = min(4 - vifX.tag.addr, vifX.vifpacketsize);
430 william 31 pxAssume(vifX.tag.addr < 4);
431     pxAssume(ret > 0);
432    
433     switch (ret) {
434     case 4:
435     pmem1[12] = data[3];
436     pmem2[3] = data[3];
437     case 3:
438     pmem1[8] = data[2];
439     pmem2[2] = data[2];
440     case 2:
441     pmem1[4] = data[1];
442     pmem2[1] = data[1];
443     case 1:
444     pmem1[0] = data[0];
445     pmem2[0] = data[0];
446     break;
447     jNO_DEFAULT
448     }
449    
450     vifX.tag.addr += ret;
451     vifX.tag.size -= ret;
452     if (!vifX.tag.size) vifX.cmd = 0;
453    
454     return ret;
455     }
456    
457     vifOp(vifCode_STCol) {
458 william 62 vifStruct& vifX = GetVifX;
459 william 31 pass1 {
460     vifX.tag.addr = 0;
461     vifX.tag.size = 4;
462     return 1;
463     }
464     pass2 {
465     u32* cols = idx ? g_vifmask.Col1 : g_vifmask.Col0;
466 william 62 u32* pmem1 = &vifXRegs.c0 + (vifX.tag.addr << 2);
467 william 31 u32* pmem2 = cols + vifX.tag.addr;
468     return _vifCode_STColRow<idx>(data, pmem1, pmem2);
469     }
470 william 62 pass3 { VifCodeLog("STCol"); }
471 william 31 return 0;
472     }
473    
474     vifOp(vifCode_STRow) {
475 william 62 vifStruct& vifX = GetVifX;
476    
477 william 31 pass1 {
478     vifX.tag.addr = 0;
479     vifX.tag.size = 4;
480     return 1;
481     }
482     pass2 {
483     u32* rows = idx ? g_vifmask.Row1 : g_vifmask.Row0;
484 william 62 u32* pmem1 = &vifXRegs.r0 + (vifX.tag.addr << 2);
485 william 31 u32* pmem2 = rows + vifX.tag.addr;
486     return _vifCode_STColRow<idx>(data, pmem1, pmem2);
487     }
488 william 62 pass3 { VifCodeLog("STRow"); }
489 william 31 return 0;
490     }
491    
492     vifOp(vifCode_STCycl) {
493 william 62 vifStruct& vifX = GetVifX;
494 william 31 pass1 {
495 william 62 vifXRegs.cycle.cl = (u8)(vifXRegs.code);
496     vifXRegs.cycle.wl = (u8)(vifXRegs.code >> 8);
497 william 31 vifX.cmd = 0;
498     }
499 william 62 pass3 { VifCodeLog("STCycl"); }
500 william 31 return 0;
501     }
502    
503     vifOp(vifCode_STMask) {
504 william 62 vifStruct& vifX = GetVifX;
505 william 31 pass1 { vifX.tag.size = 1; }
506 william 62 pass2 { vifXRegs.mask = data[0]; vifX.tag.size = 0; vifX.cmd = 0; }
507     pass3 { VifCodeLog("STMask"); }
508 william 31 return 1;
509     }
510    
511     vifOp(vifCode_STMod) {
512 william 62 pass1 { vifXRegs.mode = vifXRegs.code & 0x3; GetVifX.cmd = 0; }
513     pass3 { VifCodeLog("STMod"); }
514 william 31 return 0;
515     }
516    
517     vifOp(vifCode_Unpack) {
518     pass1 {
519 william 62 if (!idx) vifUnpackSetup<0>(data);
520     else vifUnpackSetup<1>(data);
521 william 31 return 1;
522     }
523     pass2 { return nVifUnpack(idx, (u8*)data); }
524 william 62 pass3 { VifCodeLog("Unpack"); }
525 william 31 return 0;
526     }
527    
528     //------------------------------------------------------------------
529     // Vif0/Vif1 Code Tables
530     //------------------------------------------------------------------
531    
532 william 62 __aligned16 FnType_VifCmdHandler* const vifCmdHandler[2][128] =
533     {
534     {
535     vifCode_Nop<0> , vifCode_STCycl<0> , vifCode_Offset<0> , vifCode_Base<0> , vifCode_ITop<0> , vifCode_STMod<0> , vifCode_MskPath3<0>, vifCode_Mark<0>, /*0x00*/
536     vifCode_Null<0> , vifCode_Null<0> , vifCode_Null<0> , vifCode_Null<0> , vifCode_Null<0> , vifCode_Null<0> , vifCode_Null<0> , vifCode_Null<0>, /*0x08*/
537     vifCode_FlushE<0> , vifCode_Flush<0> , vifCode_Null<0> , vifCode_FlushA<0> , vifCode_MSCAL<0> , vifCode_MSCALF<0> , vifCode_Null<0> , vifCode_MSCNT<0>, /*0x10*/
538     vifCode_Null<0> , vifCode_Null<0> , vifCode_Null<0> , vifCode_Null<0> , vifCode_Null<0> , vifCode_Null<0> , vifCode_Null<0> , vifCode_Null<0>, /*0x18*/
539     vifCode_STMask<0> , vifCode_Null<0> , vifCode_Null<0> , vifCode_Null<0> , vifCode_Null<0> , vifCode_Null<0> , vifCode_Null<0> , vifCode_Null<0>, /*0x20*/
540     vifCode_Null<0> , vifCode_Null<0> , vifCode_Null<0> , vifCode_Null<0> , vifCode_Null<0> , vifCode_Null<0> , vifCode_Null<0> , vifCode_Null<0>, /*0x28*/
541     vifCode_STRow<0> , vifCode_STCol<0> , vifCode_Null<0> , vifCode_Null<0> , vifCode_Null<0> , vifCode_Null<0> , vifCode_Null<0> , vifCode_Null<0>, /*0x30*/
542     vifCode_Null<0> , vifCode_Null<0> , vifCode_Null<0> , vifCode_Null<0> , vifCode_Null<0> , vifCode_Null<0> , vifCode_Null<0> , vifCode_Null<0>, /*0x38*/
543     vifCode_Null<0> , vifCode_Null<0> , vifCode_Null<0> , vifCode_Null<0> , vifCode_Null<0> , vifCode_Null<0> , vifCode_Null<0> , vifCode_Null<0>, /*0x40*/
544     vifCode_Null<0> , vifCode_Null<0> , vifCode_MPG<0> , vifCode_Null<0> , vifCode_Null<0> , vifCode_Null<0> , vifCode_Null<0> , vifCode_Null<0>, /*0x48*/
545     vifCode_Direct<0> , vifCode_DirectHL<0>, vifCode_Null<0> , vifCode_Null<0> , vifCode_Null<0> , vifCode_Null<0> , vifCode_Null<0> , vifCode_Null<0>, /*0x50*/
546     vifCode_Null<0> , vifCode_Null<0> , vifCode_Null<0> , vifCode_Null<0> , vifCode_Null<0> , vifCode_Null<0> , vifCode_Null<0> , vifCode_Null<0>, /*0x58*/
547     vifCode_Unpack<0> , vifCode_Unpack<0> , vifCode_Unpack<0> , vifCode_Unpack<0> , vifCode_Unpack<0> , vifCode_Unpack<0> , vifCode_Unpack<0> , vifCode_Null<0>, /*0x60*/
548     vifCode_Unpack<0> , vifCode_Unpack<0> , vifCode_Unpack<0> , vifCode_Unpack<0> , vifCode_Unpack<0> , vifCode_Unpack<0> , vifCode_Unpack<0> , vifCode_Unpack<0>, /*0x68*/
549     vifCode_Unpack<0> , vifCode_Unpack<0> , vifCode_Unpack<0> , vifCode_Unpack<0> , vifCode_Unpack<0> , vifCode_Unpack<0> , vifCode_Unpack<0> , vifCode_Null<0>, /*0x70*/
550     vifCode_Unpack<0> , vifCode_Unpack<0> , vifCode_Unpack<0> , vifCode_Null<0> , vifCode_Unpack<0> , vifCode_Unpack<0> , vifCode_Unpack<0> , vifCode_Unpack<0> /*0x78*/
551     },
552     {
553     vifCode_Nop<1> , vifCode_STCycl<1> , vifCode_Offset<1> , vifCode_Base<1> , vifCode_ITop<1> , vifCode_STMod<1> , vifCode_MskPath3<1>, vifCode_Mark<1>, /*0x00*/
554     vifCode_Null<1> , vifCode_Null<1> , vifCode_Null<1> , vifCode_Null<1> , vifCode_Null<1> , vifCode_Null<1> , vifCode_Null<1> , vifCode_Null<1>, /*0x08*/
555     vifCode_FlushE<1> , vifCode_Flush<1> , vifCode_Null<1> , vifCode_FlushA<1> , vifCode_MSCAL<1> , vifCode_MSCALF<1> , vifCode_Null<1> , vifCode_MSCNT<1>, /*0x10*/
556     vifCode_Null<1> , vifCode_Null<1> , vifCode_Null<1> , vifCode_Null<1> , vifCode_Null<1> , vifCode_Null<1> , vifCode_Null<1> , vifCode_Null<1>, /*0x18*/
557     vifCode_STMask<1> , vifCode_Null<1> , vifCode_Null<1> , vifCode_Null<1> , vifCode_Null<1> , vifCode_Null<1> , vifCode_Null<1> , vifCode_Null<1>, /*0x20*/
558     vifCode_Null<1> , vifCode_Null<1> , vifCode_Null<1> , vifCode_Null<1> , vifCode_Null<1> , vifCode_Null<1> , vifCode_Null<1> , vifCode_Null<1>, /*0x28*/
559     vifCode_STRow<1> , vifCode_STCol<1> , vifCode_Null<1> , vifCode_Null<1> , vifCode_Null<1> , vifCode_Null<1> , vifCode_Null<1> , vifCode_Null<1>, /*0x30*/
560     vifCode_Null<1> , vifCode_Null<1> , vifCode_Null<1> , vifCode_Null<1> , vifCode_Null<1> , vifCode_Null<1> , vifCode_Null<1> , vifCode_Null<1>, /*0x38*/
561     vifCode_Null<1> , vifCode_Null<1> , vifCode_Null<1> , vifCode_Null<1> , vifCode_Null<1> , vifCode_Null<1> , vifCode_Null<1> , vifCode_Null<1>, /*0x40*/
562     vifCode_Null<1> , vifCode_Null<1> , vifCode_MPG<1> , vifCode_Null<1> , vifCode_Null<1> , vifCode_Null<1> , vifCode_Null<1> , vifCode_Null<1>, /*0x48*/
563     vifCode_Direct<1> , vifCode_DirectHL<1>, vifCode_Null<1> , vifCode_Null<1> , vifCode_Null<1> , vifCode_Null<1> , vifCode_Null<1> , vifCode_Null<1>, /*0x50*/
564     vifCode_Null<1> , vifCode_Null<1> , vifCode_Null<1> , vifCode_Null<1> , vifCode_Null<1> , vifCode_Null<1> , vifCode_Null<1> , vifCode_Null<1>, /*0x58*/
565     vifCode_Unpack<1> , vifCode_Unpack<1> , vifCode_Unpack<1> , vifCode_Unpack<1> , vifCode_Unpack<1> , vifCode_Unpack<1> , vifCode_Unpack<1> , vifCode_Null<1>, /*0x60*/
566     vifCode_Unpack<1> , vifCode_Unpack<1> , vifCode_Unpack<1> , vifCode_Unpack<1> , vifCode_Unpack<1> , vifCode_Unpack<1> , vifCode_Unpack<1> , vifCode_Unpack<1>, /*0x68*/
567     vifCode_Unpack<1> , vifCode_Unpack<1> , vifCode_Unpack<1> , vifCode_Unpack<1> , vifCode_Unpack<1> , vifCode_Unpack<1> , vifCode_Unpack<1> , vifCode_Null<1>, /*0x70*/
568     vifCode_Unpack<1> , vifCode_Unpack<1> , vifCode_Unpack<1> , vifCode_Null<1> , vifCode_Unpack<1> , vifCode_Unpack<1> , vifCode_Unpack<1> , vifCode_Unpack<1> /*0x78*/
569     }
570 william 31 };

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