/[pcsx2_0.9.7]/trunk/pcsx2/Vif1_Dma.cpp
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Contents of /trunk/pcsx2/Vif1_Dma.cpp

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Revision 280 - (show annotations) (download)
Thu Dec 23 12:02:12 2010 UTC (9 years, 1 month ago) by william
File size: 13938 byte(s)
re-commit (had local access denied errors when committing)
1 /* PCSX2 - PS2 Emulator for PCs
2 * Copyright (C) 2002-2010 PCSX2 Dev Team
3 *
4 * PCSX2 is free software: you can redistribute it and/or modify it under the terms
5 * of the GNU Lesser General Public License as published by the Free Software Found-
6 * ation, either version 3 of the License, or (at your option) any later version.
7 *
8 * PCSX2 is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
9 * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
10 * PURPOSE. See the GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License along with PCSX2.
13 * If not, see <http://www.gnu.org/licenses/>.
14 */
15
16 #include "PrecompiledHeader.h"
17 #include "Common.h"
18 #include "Vif_Dma.h"
19 #include "GS.h"
20 #include "Gif.h"
21 #include "VUmicro.h"
22 #include "newVif.h"
23
24
25 __fi void vif1FLUSH()
26 {
27 if(g_packetsizeonvu > vif1.vifpacketsize && g_vu1Cycles > 0)
28 {
29 //DevCon.Warning("Adding on same packet");
30 if( ((g_packetsizeonvu - vif1.vifpacketsize) >> 1) > g_vu1Cycles)
31 g_vu1Cycles -= (g_packetsizeonvu - vif1.vifpacketsize) >> 1;
32 else g_vu1Cycles = 0;
33 }
34 if(g_vu1Cycles > 0)
35 {
36 //DevCon.Warning("Adding %x cycles to VIF1", g_vu1Cycles * BIAS);
37 g_vifCycles += g_vu1Cycles;
38 g_vu1Cycles = 0;
39
40 }
41 g_vu1Cycles = 0;//else DevCon.Warning("VIF1 Different Packet, how can i work this out :/");
42 if (VU0.VI[REG_VPU_STAT].UL & 0x100)
43 {
44 int _cycles = VU1.cycle;
45 vu1Finish();
46 //DevCon.Warning("VIF1 adding %x cycles", (VU1.cycle - _cycles) * BIAS);
47 g_vifCycles += (VU1.cycle - _cycles) * BIAS;
48 }
49 if(gifRegs.stat.P1Q && ((vif1.cmd & 0x7f) != 0x14) && ((vif1.cmd & 0x7f) != 0x17))
50 {
51 vif1.vifstalled = true;
52 vif1Regs.stat.VGW = true;
53 vif1.GifWaitState = 2;
54 }
55
56 }
57
58 void vif1TransferToMemory()
59 {
60 u32 size;
61 u128* pMem = (u128*)dmaGetAddr(vif1ch.madr, false);
62
63 // VIF from gsMemory
64 if (pMem == NULL) //Is vif0ptag empty?
65 {
66 Console.WriteLn("Vif1 Tag BUSERR");
67 dmacRegs.stat.BEIS = true; //Bus Error
68 vif1Regs.stat.FQC = 0;
69
70 vif1ch.qwc = 0;
71 vif1.done = true;
72 CPU_INT(DMAC_VIF1, 0);
73 return; //An error has occurred.
74 }
75
76 // MTGS concerns: The MTGS is inherently disagreeable with the idea of downloading
77 // stuff from the GS. The *only* way to handle this case safely is to flush the GS
78 // completely and execute the transfer there-after.
79 //Console.Warning("Real QWC %x", vif1ch.qwc);
80 size = min((u32)vif1ch.qwc, vif1.GSLastDownloadSize);
81 const u128* pMemEnd = pMem + vif1.GSLastDownloadSize;
82
83 if (GSreadFIFO2 == NULL)
84 {
85 for (;size > 0; --size)
86 {
87 GetMTGS().WaitGS();
88 GSreadFIFO((u64*)pMem);
89 ++pMem;
90 }
91 }
92 else
93 {
94 GetMTGS().WaitGS();
95 GSreadFIFO2((u64*)pMem, size);
96 pMem += size;
97 }
98
99 if(pMem < pMemEnd)
100 {
101 DevCon.Warning("GS Transfer < VIF QWC, Clearing end of space");
102
103 __m128 zeroreg = _mm_setzero_ps();
104 do {
105 _mm_store_ps((float*)pMem, zeroreg);
106 ++pMem;
107 } while (pMem < pMemEnd);
108 }
109
110 g_vifCycles += vif1ch.qwc * 2;
111 vif1ch.madr += vif1ch.qwc * 16; // mgs3 scene changes
112 if(vif1.GSLastDownloadSize >= vif1ch.qwc)
113 {
114 vif1.GSLastDownloadSize -= vif1ch.qwc;
115 vif1Regs.stat.FQC = min((u32)16, vif1.GSLastDownloadSize);
116 }
117 else
118 {
119 vif1Regs.stat.FQC = 0;
120 vif1.GSLastDownloadSize = 0;
121 }
122
123 vif1ch.qwc = 0;
124 }
125
126 bool _VIF1chain()
127 {
128 u32 *pMem;
129
130 if (vif1ch.qwc == 0)
131 {
132 vif1.inprogress &= ~1;
133 vif1.irqoffset = 0;
134 return true;
135 }
136
137 // Clarification - this is TO memory mode, for some reason i used the other way round >.<
138 if (vif1.dmamode == VIF_NORMAL_TO_MEM_MODE)
139 {
140 vif1TransferToMemory();
141 vif1.inprogress &= ~1;
142 return true;
143 }
144
145 pMem = (u32*)dmaGetAddr(vif1ch.madr, !vif1ch.chcr.DIR);
146 if (pMem == NULL)
147 {
148 vif1.cmd = 0;
149 vif1.tag.size = 0;
150 vif1ch.qwc = 0;
151 return true;
152 }
153
154 VIF_LOG("VIF1chain size=%d, madr=%lx, tadr=%lx",
155 vif1ch.qwc, vif1ch.madr, vif1ch.tadr);
156
157 if (vif1.vifstalled)
158 return VIF1transfer(pMem + vif1.irqoffset, vif1ch.qwc * 4 - vif1.irqoffset, false);
159 else
160 return VIF1transfer(pMem, vif1ch.qwc * 4, false);
161 }
162
163 __fi void vif1SetupTransfer()
164 {
165 tDMA_TAG *ptag;
166
167 switch (vif1.dmamode)
168 {
169 case VIF_NORMAL_TO_MEM_MODE:
170 case VIF_NORMAL_FROM_MEM_MODE:
171 vif1.inprogress |= 1;
172 vif1.done = true;
173 g_vifCycles = 2;
174 break;
175
176 case VIF_CHAIN_MODE:
177 ptag = dmaGetAddr(vif1ch.tadr, false); //Set memory pointer to TADR
178
179 if (!(vif1ch.transfer("Vif1 Tag", ptag))) return;
180
181 vif1ch.madr = ptag[1]._u32; //MADR = ADDR field + SPR
182 g_vifCycles += 1; // Add 1 g_vifCycles from the QW read for the tag
183
184 VIF_LOG("VIF1 Tag %8.8x_%8.8x size=%d, id=%d, madr=%lx, tadr=%lx",
185 ptag[1]._u32, ptag[0]._u32, vif1ch.qwc, ptag->ID, vif1ch.madr, vif1ch.tadr);
186
187 if (!vif1.done && ((dmacRegs.ctrl.STD == STD_VIF1) && (ptag->ID == TAG_REFS))) // STD == VIF1
188 {
189 // there are still bugs, need to also check if gif->madr +16*qwc >= stadr, if not, stall
190 if ((vif1ch.madr + vif1ch.qwc * 16) >= dmacRegs.stadr.ADDR)
191 {
192 // stalled
193 hwDmacIrq(DMAC_STALL_SIS);
194 return;
195 }
196 }
197
198
199 vif1.inprogress &= ~1;
200
201 if (vif1ch.chcr.TTE)
202 {
203 // Transfer dma tag if tte is set
204
205 bool ret;
206
207 static __aligned16 u128 masked_tag;
208
209 masked_tag._u64[0] = 0;
210 masked_tag._u64[1] = *((u64*)ptag + 1);
211
212 VIF_LOG("\tVIF1 SrcChain TTE=1, data = 0x%08x.%08x", masked_tag._u32[3], masked_tag._u32[2]);
213
214 if (vif1.vifstalled)
215 {
216 ret = VIF1transfer((u32*)&masked_tag + vif1.irqoffset, 4 - vif1.irqoffset, true); //Transfer Tag on stall
217 //ret = VIF1transfer((u32*)ptag + (2 + vif1.irqoffset), 2 - vif1.irqoffset); //Transfer Tag on stall
218 }
219 else
220 {
221 //Some games (like killzone) do Tags mid unpack, the nops will just write blank data
222 //to the VU's, which breaks stuff, this is where the 128bit packet will fail, so we ignore the first 2 words
223 vif1.irqoffset = 2;
224 ret = VIF1transfer((u32*)&masked_tag + 2, 2, true); //Transfer Tag
225 //ret = VIF1transfer((u32*)ptag + 2, 2); //Transfer Tag
226 }
227
228 if (!ret && vif1.irqoffset)
229 {
230 vif1.inprogress &= ~1; //Better clear this so it has to do it again (Jak 1)
231 return; //IRQ set by VIFTransfer
232 }
233 }
234 vif1.irqoffset = 0;
235
236 vif1.done |= hwDmacSrcChainWithStack(vif1ch, ptag->ID);
237
238 if(vif1ch.qwc > 0) vif1.inprogress |= 1;
239
240 //Check TIE bit of CHCR and IRQ bit of tag
241 if (vif1ch.chcr.TIE && ptag->IRQ)
242 {
243 VIF_LOG("dmaIrq Set");
244
245 //End Transfer
246 vif1.done = true;
247 return;
248 }
249 break;
250 }
251 }
252
253 extern bool SIGNAL_IMR_Pending;
254
255 bool CheckPath2GIF(EE_EventType channel)
256 {
257 if ((vif1Regs.stat.VGW))
258 {
259 if( vif1.GifWaitState == 0 ) //DIRECT/HL Check
260 {
261 if(GSTransferStatus.PTH3 < IDLE_MODE || gifRegs.stat.P1Q)
262 {
263 if(gifRegs.stat.IMT && GSTransferStatus.PTH3 <= IMAGE_MODE && (vif1.cmd & 0x7f) == 0x50 && gifRegs.stat.P1Q == false)
264 {
265 vif1Regs.stat.VGW = false;
266 }
267 else
268 {
269 //DevCon.Warning("VIF1-0 stall P1Q %x P2Q %x APATH %x PTH3 %x vif1cmd %x", gifRegs.stat.P1Q, gifRegs.stat.P2Q, gifRegs.stat.APATH, GSTransferStatus.PTH3, vif1.cmd);
270 CPU_INT(channel, 128);
271 return false;
272 }
273 }
274 else
275 {
276 vif1Regs.stat.VGW = false;
277 }
278 }
279 else if( vif1.GifWaitState == 1 ) // Else we're flushing path3 :), but of course waiting for the microprogram to finish
280 {
281 if (gifRegs.stat.P1Q)
282 {
283 //DevCon.Warning("VIF1-1 stall P1Q %x P2Q %x APATH %x PTH3 %x vif1cmd %x", gifRegs.stat.P1Q, gifRegs.stat.P2Q, gifRegs.stat.APATH, GSTransferStatus.PTH3, vif1.cmd);
284 CPU_INT(channel, 128);
285 return false;
286 }
287
288 if (GSTransferStatus.PTH3 < IDLE_MODE)
289 {
290 //DevCon.Warning("VIF1-11 stall P1Q %x P2Q %x APATH %x PTH3 %x vif1cmd %x", gifRegs.stat.P1Q, gifRegs.stat.P2Q, gifRegs.stat.APATH, GSTransferStatus.PTH3, vif1.cmd);
291 //DevCon.Warning("PTH3 %x P1Q %x P3Q %x IP3 %x", GSTransferStatus.PTH3, gifRegs.stat.P1Q, gifRegs.stat.P3Q, gifRegs.stat.IP3 );
292 CPU_INT(channel, 8);
293 return false;
294 }
295 else
296 {
297 vif1Regs.stat.VGW = false;
298 }
299 }
300 else if( vif1.GifWaitState == 3 ) // Else we're flushing path3 :), but of course waiting for the microprogram to finish
301 {
302 if (gifRegs.ctrl.PSE)
303 {
304 //DevCon.Warning("VIF1-1 stall P1Q %x P2Q %x APATH %x PTH3 %x vif1cmd %x", gifRegs.stat.P1Q, gifRegs.stat.P2Q, gifRegs.stat.APATH, GSTransferStatus.PTH3, vif1.cmd);
305 CPU_INT(channel, 128);
306 return false;
307 }
308 else
309 {
310 vif1Regs.stat.VGW = false;
311 }
312 }
313 else //Normal Flush
314 {
315 if (gifRegs.stat.P1Q)
316 {
317 //DevCon.Warning("VIF1-2 stall P1Q %x P2Q %x APATH %x PTH3 %x vif1cmd %x", gifRegs.stat.P1Q, gifRegs.stat.P2Q, gifRegs.stat.APATH, GSTransferStatus.PTH3, vif1.cmd);
318 CPU_INT(channel, 128);
319 return false;
320 }
321 else
322 {
323 vif1Regs.stat.VGW = false;
324 }
325 }
326 }
327 if(SIGNAL_IMR_Pending == true && (vif1.cmd & 0x7e) == 0x50)
328 {
329 //DevCon.Warning("Path 2 Paused");
330 CPU_INT(channel, 128);
331 return false;
332 }
333 return true;
334 }
335 __fi void vif1Interrupt()
336 {
337 VIF_LOG("vif1Interrupt: %8.8x", cpuRegs.cycle);
338
339 g_vifCycles = 0;
340
341 if(GSTransferStatus.PTH2 == STOPPED_MODE && gifRegs.stat.APATH == GIF_APATH2)
342 {
343 gifRegs.stat.OPH = false;
344 gifRegs.stat.APATH = GIF_APATH_IDLE;
345 if(gifRegs.stat.P1Q) gsPath1Interrupt();
346 }
347
348 if (schedulepath3msk & 0x10)
349 {
350 Vif1MskPath3();
351 CPU_INT(DMAC_VIF1, 8);
352 return;
353 }
354 //Some games (Fahrenheit being one) start vif first, let it loop through blankness while it sets MFIFO mode, so we need to check it here.
355 if (dmacRegs.ctrl.MFD == MFD_VIF1)
356 {
357 //Console.WriteLn("VIFMFIFO\n");
358 // Test changed because the Final Fantasy 12 opening somehow has the tag in *Undefined* mode, which is not in the documentation that I saw.
359 if (vif1ch.chcr.MOD == NORMAL_MODE) Console.WriteLn("MFIFO mode is normal (which isn't normal here)! %x", vif1ch.chcr._u32);
360 vif1Regs.stat.FQC = min((u16)0x10, vif1ch.qwc);
361 vifMFIFOInterrupt();
362 return;
363 }
364
365 //We need to check the direction, if it is downloading from the GS, we handle that separately (KH2 for testing)
366 if (vif1ch.chcr.DIR)
367 {
368 if (!CheckPath2GIF(DMAC_VIF1)) return;
369
370 vif1Regs.stat.FQC = min(vif1ch.qwc, (u16)16);
371 //Simulated GS transfer time done, clear the flags
372 }
373
374 if (!vif1ch.chcr.STR) Console.WriteLn("Vif1 running when CHCR == %x", vif1ch.chcr._u32);
375
376 if (vif1.cmd)
377 {
378 if (vif1.done && (vif1ch.qwc == 0)) vif1Regs.stat.VPS = VPS_WAITING;
379 }
380 else
381 {
382 vif1Regs.stat.VPS = VPS_IDLE;
383 }
384
385 if (vif1.irq && vif1.tag.size == 0)
386 {
387 vif1Regs.stat.INT = true;
388 hwIntcIrq(VIF1intc);
389 --vif1.irq;
390 if (vif1Regs.stat.test(VIF1_STAT_VSS | VIF1_STAT_VIS | VIF1_STAT_VFS))
391 {
392 //vif1Regs.stat.FQC = 0;
393
394 //NFSHPS stalls when the whole packet has gone across (it stalls in the last 32bit cmd)
395 //In this case VIF will end
396 if(vif1ch.qwc > 0 || !vif1.done) return;
397 }
398 }
399
400 if (vif1.inprogress & 0x1)
401 {
402 _VIF1chain();
403 // VIF_NORMAL_FROM_MEM_MODE is a very slow operation.
404 // Timesplitters 2 depends on this beeing a bit higher than 128.
405 if (vif1ch.chcr.DIR) vif1Regs.stat.FQC = min(vif1ch.qwc, (u16)16);
406 // Refraction - Removing voodoo timings for now, completely messes a lot of Path3 masked games.
407 /*if (vif1.dmamode == VIF_NORMAL_FROM_MEM_MODE ) CPU_INT(DMAC_VIF1, 1024);
408 else */CPU_INT(DMAC_VIF1, g_vifCycles /*VifCycleVoodoo*/);
409 return;
410 }
411
412 if (!vif1.done)
413 {
414
415 if (!(dmacRegs.ctrl.DMAE))
416 {
417 Console.WriteLn("vif1 dma masked");
418 return;
419 }
420
421 if ((vif1.inprogress & 0x1) == 0) vif1SetupTransfer();
422 if (vif1ch.chcr.DIR) vif1Regs.stat.FQC = min(vif1ch.qwc, (u16)16);
423 CPU_INT(DMAC_VIF1, g_vifCycles);
424 return;
425 }
426
427 if (vif1.vifstalled && vif1.irq)
428 {
429 DevCon.WriteLn("VIF1 looping on stall\n");
430 CPU_INT(DMAC_VIF1, 0);
431 return; //Dont want to end if vif is stalled.
432 }
433 #ifdef PCSX2_DEVBUILD
434 if (vif1ch.qwc > 0) Console.WriteLn("VIF1 Ending with %x QWC left", vif1ch.qwc);
435 if (vif1.cmd != 0) Console.WriteLn("vif1.cmd still set %x tag size %x", vif1.cmd, vif1.tag.size);
436 #endif
437
438 if((vif1ch.chcr.DIR == VIF_NORMAL_TO_MEM_MODE) && vif1.GSLastDownloadSize <= 16)
439 {
440 //Reverse fifo has finished and nothing is left, so lets clear the outputting flag
441 gifRegs.stat.OPH = false;
442 }
443
444 vif1ch.chcr.STR = false;
445 vif1.vifstalled = false;
446 g_vifCycles = 0;
447 g_vu1Cycles = 0;
448 VIF_LOG("VIF1 End");
449 hwDmacIrq(DMAC_VIF1);
450
451 }
452
453 void dmaVIF1()
454 {
455 VIF_LOG("dmaVIF1 chcr = %lx, madr = %lx, qwc = %lx\n"
456 " tadr = %lx, asr0 = %lx, asr1 = %lx",
457 vif1ch.chcr._u32, vif1ch.madr, vif1ch.qwc,
458 vif1ch.tadr, vif1ch.asr0, vif1ch.asr1);
459
460 // vif1.done = false;
461
462 //if(vif1.irqoffset != 0 && vif1.vifstalled == true) DevCon.Warning("Offset on VIF1 start! offset %x, Progress %x", vif1.irqoffset, vif1.vifstalled);
463 /*vif1.irqoffset = 0;
464 vif1.vifstalled = false;
465 vif1.inprogress = 0;*/
466 g_vifCycles = 0;
467 g_vu1Cycles = 0;
468
469 #ifdef PCSX2_DEVBUILD
470 if (dmacRegs.ctrl.STD == STD_VIF1)
471 {
472 //DevCon.WriteLn("VIF Stall Control Source = %x, Drain = %x", (psHu32(0xe000) >> 4) & 0x3, (psHu32(0xe000) >> 6) & 0x3);
473 }
474 #endif
475
476 if ((vif1ch.chcr.MOD == NORMAL_MODE) || vif1ch.qwc > 0) // Normal Mode
477 {
478
479 if (dmacRegs.ctrl.STD == STD_VIF1)
480 Console.WriteLn("DMA Stall Control on VIF1 normal");
481
482 if (vif1ch.chcr.DIR) // to Memory
483 vif1.dmamode = VIF_NORMAL_FROM_MEM_MODE;
484 else
485 vif1.dmamode = VIF_NORMAL_TO_MEM_MODE;
486
487 vif1.done = false;
488
489 // ignore tag if it's a GS download (Def Jam Fight for NY)
490 if(vif1ch.chcr.MOD == CHAIN_MODE && vif1.dmamode != VIF_NORMAL_TO_MEM_MODE)
491 {
492 vif1.dmamode = VIF_CHAIN_MODE;
493 //DevCon.Warning(L"VIF1 QWC on Chain CHCR " + vif1ch.chcr.desc());
494
495 if ((vif1ch.chcr.tag().ID == TAG_REFE) || (vif1ch.chcr.tag().ID == TAG_END))
496 {
497 vif1.done = true;
498 }
499 }
500 }
501 else
502 {
503 vif1.dmamode = VIF_CHAIN_MODE;
504 vif1.done = false;
505 vif1.inprogress = 0;
506 }
507
508 if (vif1ch.chcr.DIR) vif1Regs.stat.FQC = min((u16)0x10, vif1ch.qwc);
509
510 // Chain Mode
511 CPU_INT(DMAC_VIF1, 4);
512 }

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