/[pcsx2_0.9.7]/trunk/pcsx2/Vif1_Dma.cpp
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Annotation of /trunk/pcsx2/Vif1_Dma.cpp

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Revision 87 - (hide annotations) (download)
Wed Sep 8 12:10:38 2010 UTC (9 years, 10 months ago) by william
File size: 13294 byte(s)
Auto Commited Import of: pcsx2-0.9.7-r3741-debug in ./trunk
1 william 31 /* PCSX2 - PS2 Emulator for PCs
2     * Copyright (C) 2002-2010 PCSX2 Dev Team
3     *
4     * PCSX2 is free software: you can redistribute it and/or modify it under the terms
5     * of the GNU Lesser General Public License as published by the Free Software Found-
6     * ation, either version 3 of the License, or (at your option) any later version.
7     *
8     * PCSX2 is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
9     * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
10     * PURPOSE. See the GNU General Public License for more details.
11     *
12     * You should have received a copy of the GNU General Public License along with PCSX2.
13     * If not, see <http://www.gnu.org/licenses/>.
14     */
15    
16     #include "PrecompiledHeader.h"
17     #include "Common.h"
18     #include "Vif_Dma.h"
19     #include "GS.h"
20     #include "Gif.h"
21     #include "VUmicro.h"
22     #include "newVif.h"
23    
24 william 62
25     __fi void vif1FLUSH()
26 william 31 {
27 william 62 if(g_packetsizeonvu > vif1.vifpacketsize && g_vu1Cycles > 0)
28     {
29     //DevCon.Warning("Adding on same packet");
30     if( ((g_packetsizeonvu - vif1.vifpacketsize) >> 1) > g_vu1Cycles)
31     g_vu1Cycles -= (g_packetsizeonvu - vif1.vifpacketsize) >> 1;
32     else g_vu1Cycles = 0;
33     }
34     if(g_vu1Cycles > 0)
35     {
36     //DevCon.Warning("Adding %x cycles to VIF1", g_vu1Cycles * BIAS);
37     g_vifCycles += g_vu1Cycles;
38     g_vu1Cycles = 0;
39    
40     }
41     g_vu1Cycles = 0;//else DevCon.Warning("VIF1 Different Packet, how can i work this out :/");
42     if (VU0.VI[REG_VPU_STAT].UL & 0x100)
43     {
44     int _cycles = VU1.cycle;
45     vu1Finish();
46     //DevCon.Warning("VIF1 adding %x cycles", (VU1.cycle - _cycles) * BIAS);
47     g_vifCycles += (VU1.cycle - _cycles) * BIAS;
48     }
49     if(gifRegs.stat.P1Q && ((vif1.cmd & 0x7f) != 0x14) && ((vif1.cmd & 0x7f) != 0x17))
50     {
51     vif1.vifstalled = true;
52     vif1Regs.stat.VGW = true;
53     vif1.GifWaitState = 2;
54     }
55    
56 william 31 }
57    
58     void vif1TransferToMemory()
59     {
60     u32 size;
61 william 87 u128* pMem = (u128*)dmaGetAddr(vif1ch.madr, false);
62 william 31
63     // VIF from gsMemory
64     if (pMem == NULL) //Is vif0ptag empty?
65     {
66     Console.WriteLn("Vif1 Tag BUSERR");
67 william 62 dmacRegs.stat.BEIS = true; //Bus Error
68     vif1Regs.stat.FQC = 0;
69 william 31
70 william 62 vif1ch.qwc = 0;
71 william 31 vif1.done = true;
72     CPU_INT(DMAC_VIF1, 0);
73     return; //An error has occurred.
74     }
75    
76     // MTGS concerns: The MTGS is inherently disagreeable with the idea of downloading
77     // stuff from the GS. The *only* way to handle this case safely is to flush the GS
78     // completely and execute the transfer there-after.
79 william 62 //Console.Warning("Real QWC %x", vif1ch.qwc);
80     size = min((u32)vif1ch.qwc, vif1.GSLastDownloadSize);
81 william 87 const u128* pMemEnd = pMem + vif1.GSLastDownloadSize;
82 william 31
83     if (GSreadFIFO2 == NULL)
84     {
85     for (;size > 0; --size)
86     {
87     GetMTGS().WaitGS();
88 william 87 GSreadFIFO((u64*)pMem);
89     ++pMem;
90 william 31 }
91     }
92     else
93     {
94     GetMTGS().WaitGS();
95 william 87 GSreadFIFO2((u64*)pMem, size);
96     pMem += size;
97     }
98 william 31
99 william 87 if(pMem < pMemEnd)
100     {
101     DevCon.Warning("GS Transfer < VIF QWC, Clearing end of space");
102    
103     __m128 zeroreg = _mm_setzero_ps();
104     do {
105     _mm_store_ps((float*)pMem, zeroreg);
106     ++pMem;
107     } while (pMem < pMemEnd);
108 william 31 }
109    
110 william 62 g_vifCycles += vif1ch.qwc * 2;
111     vif1ch.madr += vif1ch.qwc * 16; // mgs3 scene changes
112     if(vif1.GSLastDownloadSize >= vif1ch.qwc)
113 william 31 {
114 william 62 vif1.GSLastDownloadSize -= vif1ch.qwc;
115     vif1Regs.stat.FQC = min((u32)16, vif1.GSLastDownloadSize);
116 william 31 }
117     else
118     {
119 william 62 vif1Regs.stat.FQC = 0;
120 william 31 vif1.GSLastDownloadSize = 0;
121     }
122    
123 william 62 vif1ch.qwc = 0;
124 william 31 }
125    
126     bool _VIF1chain()
127     {
128     u32 *pMem;
129    
130 william 62 if (vif1ch.qwc == 0)
131 william 31 {
132 william 62 vif1.inprogress &= ~1;
133     vif1.irqoffset = 0;
134 william 31 return true;
135     }
136    
137     // Clarification - this is TO memory mode, for some reason i used the other way round >.<
138     if (vif1.dmamode == VIF_NORMAL_TO_MEM_MODE)
139     {
140     vif1TransferToMemory();
141 william 62 vif1.inprogress &= ~1;
142 william 31 return true;
143     }
144    
145 william 62 pMem = (u32*)dmaGetAddr(vif1ch.madr, !vif1ch.chcr.DIR);
146 william 31 if (pMem == NULL)
147     {
148     vif1.cmd = 0;
149     vif1.tag.size = 0;
150 william 62 vif1ch.qwc = 0;
151 william 31 return true;
152     }
153    
154     VIF_LOG("VIF1chain size=%d, madr=%lx, tadr=%lx",
155 william 62 vif1ch.qwc, vif1ch.madr, vif1ch.tadr);
156 william 31
157     if (vif1.vifstalled)
158 william 62 return VIF1transfer(pMem + vif1.irqoffset, vif1ch.qwc * 4 - vif1.irqoffset);
159 william 31 else
160 william 62 return VIF1transfer(pMem, vif1ch.qwc * 4);
161 william 31 }
162    
163 william 62 __fi void vif1SetupTransfer()
164 william 31 {
165     tDMA_TAG *ptag;
166 william 62
167 william 31 switch (vif1.dmamode)
168     {
169     case VIF_NORMAL_TO_MEM_MODE:
170     case VIF_NORMAL_FROM_MEM_MODE:
171 william 62 vif1.inprogress |= 1;
172 william 31 vif1.done = true;
173     g_vifCycles = 2;
174 william 62 break;
175 william 31
176     case VIF_CHAIN_MODE:
177 william 62 ptag = dmaGetAddr(vif1ch.tadr, false); //Set memory pointer to TADR
178 william 31
179 william 62 if (!(vif1ch.transfer("Vif1 Tag", ptag))) return;
180 william 31
181 william 62 vif1ch.madr = ptag[1]._u32; //MADR = ADDR field + SPR
182 william 31 g_vifCycles += 1; // Add 1 g_vifCycles from the QW read for the tag
183    
184 william 62 VIF_LOG("VIF1 Tag %8.8x_%8.8x size=%d, id=%d, madr=%lx, tadr=%lx",
185     ptag[1]._u32, ptag[0]._u32, vif1ch.qwc, ptag->ID, vif1ch.madr, vif1ch.tadr);
186 william 31
187 william 62 if (!vif1.done && ((dmacRegs.ctrl.STD == STD_VIF1) && (ptag->ID == TAG_REFS))) // STD == VIF1
188 william 31 {
189     // there are still bugs, need to also check if gif->madr +16*qwc >= stadr, if not, stall
190 william 62 if ((vif1ch.madr + vif1ch.qwc * 16) >= dmacRegs.stadr.ADDR)
191 william 31 {
192     // stalled
193     hwDmacIrq(DMAC_STALL_SIS);
194     return;
195     }
196     }
197    
198 william 62
199     vif1.inprogress &= ~1;
200 william 31
201 william 62 if (vif1ch.chcr.TTE)
202 william 31 {
203 william 62 // Transfer dma tag if tte is set
204    
205 william 31 bool ret;
206    
207     if (vif1.vifstalled)
208 william 62 {
209     ret = VIF1transfer((u32*)ptag + (2 + vif1.irqoffset), 2 - vif1.irqoffset); //Transfer Tag on stall
210     }
211 william 31 else
212 william 62 ret = VIF1transfer((u32*)ptag + 2, 2); //Transfer Tag
213    
214     if (!ret && vif1.irqoffset < 2)
215 william 31 {
216 william 62 vif1.inprogress &= ~1; //Better clear this so it has to do it again (Jak 1)
217     return; //IRQ set by VIFTransfer
218    
219     } //else vif1.vifstalled = false;
220 william 31 }
221 william 62 vif1.irqoffset = 0;
222 william 31
223     vif1.done |= hwDmacSrcChainWithStack(vif1ch, ptag->ID);
224    
225 william 62 if(vif1ch.qwc > 0) vif1.inprogress |= 1;
226    
227 william 31 //Check TIE bit of CHCR and IRQ bit of tag
228 william 62 if (vif1ch.chcr.TIE && ptag->IRQ)
229 william 31 {
230     VIF_LOG("dmaIrq Set");
231    
232     //End Transfer
233     vif1.done = true;
234     return;
235     }
236 william 62 break;
237 william 31 }
238     }
239    
240 william 62 extern bool SIGNAL_IMR_Pending;
241    
242     bool CheckPath2GIF(EE_EventType channel)
243 william 31 {
244 william 62 if ((vif1Regs.stat.VGW))
245     {
246     if( vif1.GifWaitState == 0 ) //DIRECT/HL Check
247     {
248     if(GSTransferStatus.PTH3 < IDLE_MODE || gifRegs.stat.P1Q)
249     {
250     if(gifRegs.stat.IMT && GSTransferStatus.PTH3 <= IMAGE_MODE && (vif1.cmd & 0x7f) == 0x50 && gifRegs.stat.P1Q == false)
251     {
252     vif1Regs.stat.VGW = false;
253     }
254     else
255     {
256     //DevCon.Warning("VIF1-0 stall P1Q %x P2Q %x APATH %x PTH3 %x vif1cmd %x", gifRegs.stat.P1Q, gifRegs.stat.P2Q, gifRegs.stat.APATH, GSTransferStatus.PTH3, vif1.cmd);
257     CPU_INT(channel, 128);
258     return false;
259     }
260     }
261     else
262     {
263     vif1Regs.stat.VGW = false;
264     }
265     }
266     else if( vif1.GifWaitState == 1 ) // Else we're flushing path3 :), but of course waiting for the microprogram to finish
267     {
268     if (gifRegs.stat.P1Q)
269     {
270     //DevCon.Warning("VIF1-1 stall P1Q %x P2Q %x APATH %x PTH3 %x vif1cmd %x", gifRegs.stat.P1Q, gifRegs.stat.P2Q, gifRegs.stat.APATH, GSTransferStatus.PTH3, vif1.cmd);
271     CPU_INT(channel, 128);
272     return false;
273     }
274    
275     if (GSTransferStatus.PTH3 < IDLE_MODE)
276     {
277     //DevCon.Warning("VIF1-11 stall P1Q %x P2Q %x APATH %x PTH3 %x vif1cmd %x", gifRegs.stat.P1Q, gifRegs.stat.P2Q, gifRegs.stat.APATH, GSTransferStatus.PTH3, vif1.cmd);
278     //DevCon.Warning("PTH3 %x P1Q %x P3Q %x IP3 %x", GSTransferStatus.PTH3, gifRegs.stat.P1Q, gifRegs.stat.P3Q, gifRegs.stat.IP3 );
279     CPU_INT(channel, 8);
280     return false;
281     }
282     else
283     {
284     vif1Regs.stat.VGW = false;
285     }
286     }
287     else if( vif1.GifWaitState == 3 ) // Else we're flushing path3 :), but of course waiting for the microprogram to finish
288     {
289     if (gifRegs.ctrl.PSE)
290     {
291     //DevCon.Warning("VIF1-1 stall P1Q %x P2Q %x APATH %x PTH3 %x vif1cmd %x", gifRegs.stat.P1Q, gifRegs.stat.P2Q, gifRegs.stat.APATH, GSTransferStatus.PTH3, vif1.cmd);
292     CPU_INT(channel, 128);
293     return false;
294     }
295     else
296     {
297     vif1Regs.stat.VGW = false;
298     }
299     }
300     else //Normal Flush
301     {
302     if (gifRegs.stat.P1Q)
303     {
304     //DevCon.Warning("VIF1-2 stall P1Q %x P2Q %x APATH %x PTH3 %x vif1cmd %x", gifRegs.stat.P1Q, gifRegs.stat.P2Q, gifRegs.stat.APATH, GSTransferStatus.PTH3, vif1.cmd);
305     CPU_INT(channel, 128);
306     return false;
307     }
308     else
309     {
310     vif1Regs.stat.VGW = false;
311     }
312     }
313     }
314     if(SIGNAL_IMR_Pending == true && (vif1.cmd & 0x7e) == 0x50)
315     {
316     //DevCon.Warning("Path 2 Paused");
317     CPU_INT(channel, 128);
318     return false;
319     }
320     return true;
321     }
322     __fi void vif1Interrupt()
323     {
324 william 31 VIF_LOG("vif1Interrupt: %8.8x", cpuRegs.cycle);
325    
326     g_vifCycles = 0;
327    
328 william 62 if(GSTransferStatus.PTH2 == STOPPED_MODE && gifRegs.stat.APATH == GIF_APATH2)
329     {
330     gifRegs.stat.OPH = false;
331     gifRegs.stat.APATH = GIF_APATH_IDLE;
332     if(gifRegs.stat.P1Q) gsPath1Interrupt();
333     }
334    
335     if (schedulepath3msk & 0x10)
336     {
337     Vif1MskPath3();
338     CPU_INT(DMAC_VIF1, 8);
339     return;
340     }
341 william 31 //Some games (Fahrenheit being one) start vif first, let it loop through blankness while it sets MFIFO mode, so we need to check it here.
342 william 62 if (dmacRegs.ctrl.MFD == MFD_VIF1)
343 william 31 {
344     //Console.WriteLn("VIFMFIFO\n");
345     // Test changed because the Final Fantasy 12 opening somehow has the tag in *Undefined* mode, which is not in the documentation that I saw.
346 william 62 if (vif1ch.chcr.MOD == NORMAL_MODE) Console.WriteLn("MFIFO mode is normal (which isn't normal here)! %x", vif1ch.chcr._u32);
347     vif1Regs.stat.FQC = min((u16)0x10, vif1ch.qwc);
348 william 31 vifMFIFOInterrupt();
349     return;
350     }
351    
352 william 62 //We need to check the direction, if it is downloading from the GS, we handle that separately (KH2 for testing)
353     if (vif1ch.chcr.DIR)
354 william 31 {
355 william 62 if (!CheckPath2GIF(DMAC_VIF1)) return;
356    
357     vif1Regs.stat.FQC = min(vif1ch.qwc, (u16)16);
358     //Simulated GS transfer time done, clear the flags
359 william 31 }
360 william 62
361     if (!vif1ch.chcr.STR) Console.WriteLn("Vif1 running when CHCR == %x", vif1ch.chcr._u32);
362 william 31
363 william 62 if (vif1.cmd)
364 william 31 {
365 william 62 if (vif1.done && (vif1ch.qwc == 0)) vif1Regs.stat.VPS = VPS_WAITING;
366 william 31 }
367 william 62 else
368     {
369     vif1Regs.stat.VPS = VPS_IDLE;
370     }
371 william 31
372     if (vif1.irq && vif1.tag.size == 0)
373     {
374 william 62 vif1Regs.stat.INT = true;
375 william 31 hwIntcIrq(VIF1intc);
376     --vif1.irq;
377 william 62 if (vif1Regs.stat.test(VIF1_STAT_VSS | VIF1_STAT_VIS | VIF1_STAT_VFS))
378 william 31 {
379 william 62 //vif1Regs.stat.FQC = 0;
380 william 31
381 william 62 //NFSHPS stalls when the whole packet has gone across (it stalls in the last 32bit cmd)
382     //In this case VIF will end
383     if(vif1ch.qwc > 0 || !vif1.done) return;
384 william 31 }
385     }
386    
387     if (vif1.inprogress & 0x1)
388     {
389     _VIF1chain();
390     // VIF_NORMAL_FROM_MEM_MODE is a very slow operation.
391     // Timesplitters 2 depends on this beeing a bit higher than 128.
392 william 62 if (vif1ch.chcr.DIR) vif1Regs.stat.FQC = min(vif1ch.qwc, (u16)16);
393 william 31 // Refraction - Removing voodoo timings for now, completely messes a lot of Path3 masked games.
394     /*if (vif1.dmamode == VIF_NORMAL_FROM_MEM_MODE ) CPU_INT(DMAC_VIF1, 1024);
395     else */CPU_INT(DMAC_VIF1, g_vifCycles /*VifCycleVoodoo*/);
396     return;
397     }
398    
399     if (!vif1.done)
400     {
401    
402 william 62 if (!(dmacRegs.ctrl.DMAE))
403 william 31 {
404     Console.WriteLn("vif1 dma masked");
405     return;
406     }
407    
408     if ((vif1.inprogress & 0x1) == 0) vif1SetupTransfer();
409 william 62 if (vif1ch.chcr.DIR) vif1Regs.stat.FQC = min(vif1ch.qwc, (u16)16);
410 william 31 CPU_INT(DMAC_VIF1, g_vifCycles);
411     return;
412     }
413    
414     if (vif1.vifstalled && vif1.irq)
415     {
416     DevCon.WriteLn("VIF1 looping on stall\n");
417     CPU_INT(DMAC_VIF1, 0);
418     return; //Dont want to end if vif is stalled.
419     }
420     #ifdef PCSX2_DEVBUILD
421 william 62 if (vif1ch.qwc > 0) Console.WriteLn("VIF1 Ending with %x QWC left", vif1ch.qwc);
422 william 31 if (vif1.cmd != 0) Console.WriteLn("vif1.cmd still set %x tag size %x", vif1.cmd, vif1.tag.size);
423     #endif
424    
425 william 62 if((vif1ch.chcr.DIR == VIF_NORMAL_TO_MEM_MODE) && vif1.GSLastDownloadSize <= 16)
426     {
427     //Reverse fifo has finished and nothing is left, so lets clear the outputting flag
428     gifRegs.stat.OPH = false;
429 william 31 }
430 william 62
431     vif1ch.chcr.STR = false;
432     vif1.vifstalled = false;
433 william 31 g_vifCycles = 0;
434 william 62 g_vu1Cycles = 0;
435 william 31 VIF_LOG("VIF1 End");
436     hwDmacIrq(DMAC_VIF1);
437    
438     }
439    
440     void dmaVIF1()
441     {
442     VIF_LOG("dmaVIF1 chcr = %lx, madr = %lx, qwc = %lx\n"
443     " tadr = %lx, asr0 = %lx, asr1 = %lx",
444 william 62 vif1ch.chcr._u32, vif1ch.madr, vif1ch.qwc,
445     vif1ch.tadr, vif1ch.asr0, vif1ch.asr1);
446 william 31
447 william 62 // vif1.done = false;
448    
449     //if(vif1.irqoffset != 0 && vif1.vifstalled == true) DevCon.Warning("Offset on VIF1 start! offset %x, Progress %x", vif1.irqoffset, vif1.vifstalled);
450     /*vif1.irqoffset = 0;
451     vif1.vifstalled = false;
452     vif1.inprogress = 0;*/
453 william 31 g_vifCycles = 0;
454 william 62 g_vu1Cycles = 0;
455 william 31
456     #ifdef PCSX2_DEVBUILD
457 william 62 if (dmacRegs.ctrl.STD == STD_VIF1)
458 william 31 {
459     //DevCon.WriteLn("VIF Stall Control Source = %x, Drain = %x", (psHu32(0xe000) >> 4) & 0x3, (psHu32(0xe000) >> 6) & 0x3);
460     }
461     #endif
462    
463 william 62 if ((vif1ch.chcr.MOD == NORMAL_MODE) || vif1ch.qwc > 0) // Normal Mode
464 william 31 {
465    
466 william 62 if (dmacRegs.ctrl.STD == STD_VIF1)
467 william 31 Console.WriteLn("DMA Stall Control on VIF1 normal");
468    
469 william 62 if (vif1ch.chcr.DIR) // to Memory
470 william 31 vif1.dmamode = VIF_NORMAL_FROM_MEM_MODE;
471     else
472     vif1.dmamode = VIF_NORMAL_TO_MEM_MODE;
473    
474 william 62 vif1.done = false;
475    
476     // ignore tag if it's a GS download (Def Jam Fight for NY)
477     if(vif1ch.chcr.MOD == CHAIN_MODE && vif1.dmamode != VIF_NORMAL_TO_MEM_MODE)
478     {
479     vif1.dmamode = VIF_CHAIN_MODE;
480     DevCon.Warning(L"VIF1 QWC on Chain CHCR " + vif1ch.chcr.desc());
481    
482     if ((vif1ch.chcr.tag().ID == TAG_REFE) || (vif1ch.chcr.tag().ID == TAG_END))
483     {
484     vif1.done = true;
485     }
486     }
487 william 31 }
488     else
489     {
490     vif1.dmamode = VIF_CHAIN_MODE;
491 william 62 vif1.done = false;
492 william 31 }
493    
494 william 62 if (vif1ch.chcr.DIR) vif1Regs.stat.FQC = min((u16)0x10, vif1ch.qwc);
495 william 31
496     // Chain Mode
497 william 62 CPU_INT(DMAC_VIF1, 4);
498 william 31 }

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