/[pcsx2_0.9.7]/trunk/pcsx2/Vif.h
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Annotation of /trunk/pcsx2/Vif.h

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Revision 273 - (hide annotations) (download)
Fri Nov 12 01:10:22 2010 UTC (9 years, 3 months ago) by william
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Auto Commited Import of: pcsx2-0.9.7-DEBUG (upstream: v0.9.7.4013 local: v0.9.7.197-latest) in ./trunk
1 william 31 /* PCSX2 - PS2 Emulator for PCs
2     * Copyright (C) 2002-2010 PCSX2 Dev Team
3     *
4     * PCSX2 is free software: you can redistribute it and/or modify it under the terms
5     * of the GNU Lesser General Public License as published by the Free Software Found-
6     * ation, either version 3 of the License, or (at your option) any later version.
7     *
8     * PCSX2 is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
9     * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
10     * PURPOSE. See the GNU General Public License for more details.
11     *
12     * You should have received a copy of the GNU General Public License along with PCSX2.
13     * If not, see <http://www.gnu.org/licenses/>.
14     */
15    
16     #pragma once
17    
18 william 62 #include "MemoryTypes.h"
19     #include "R5900.h"
20    
21 william 31 enum vif0_stat_flags
22     {
23     VIF0_STAT_VPS_W = (1),
24     VIF0_STAT_VPS_D = (2),
25     VIF0_STAT_VPS_T = (3),
26     VIF0_STAT_VPS = (3),
27     VIF0_STAT_VEW = (1<<2),
28     VIF0_STAT_MRK = (1<<6),
29     VIF0_STAT_DBF = (1<<7),
30     VIF0_STAT_VSS = (1<<8),
31     VIF0_STAT_VFS = (1<<9),
32     VIF0_STAT_VIS = (1<<10),
33     VIF0_STAT_INT = (1<<11),
34     VIF0_STAT_ER0 = (1<<12),
35     VIF0_STAT_ER1 = (1<<13),
36     VIF0_STAT_FQC = (15<<24)
37     };
38    
39     enum vif1_stat_flags
40     {
41     VIF1_STAT_VPS_W = (1),
42     VIF1_STAT_VPS_D = (2),
43     VIF1_STAT_VPS_T = (3),
44     VIF1_STAT_VPS = (3),
45     VIF1_STAT_VEW = (1<<2),
46     VIF1_STAT_VGW = (1<<3),
47     VIF1_STAT_MRK = (1<<6),
48     VIF1_STAT_DBF = (1<<7),
49     VIF1_STAT_VSS = (1<<8),
50     VIF1_STAT_VFS = (1<<9),
51     VIF1_STAT_VIS = (1<<10),
52     VIF1_STAT_INT = (1<<11),
53     VIF1_STAT_ER0 = (1<<12),
54     VIF1_STAT_ER1 = (1<<13),
55     VIF1_STAT_FDR = (1<<23),
56     VIF1_STAT_FQC = (31<<24)
57     };
58    
59     // These are the stat flags that are the same for vif0 & vif1,
60     // for occassions where we don't neccessarily know which we are using.
61     enum vif_stat_flags
62     {
63     VIF_STAT_VPS_W = (1),
64     VIF_STAT_VPS_D = (2),
65     VIF_STAT_VPS_T = (3),
66     VIF_STAT_VPS = (3),
67     VIF_STAT_VEW = (1<<2),
68     VIF_STAT_MRK = (1<<6),
69     VIF_STAT_DBF = (1<<7),
70     VIF_STAT_VSS = (1<<8),
71     VIF_STAT_VFS = (1<<9),
72     VIF_STAT_VIS = (1<<10),
73     VIF_STAT_INT = (1<<11),
74     VIF_STAT_ER0 = (1<<12),
75     VIF_STAT_ER1 = (1<<13)
76     };
77    
78     enum vif_status
79     {
80     VPS_IDLE = 0,
81     VPS_WAITING = 1,
82     VPS_DECODING = 2,
83     VPS_TRANSFERRING = 3 // And decompressing.
84     };
85    
86     //
87     // Bitfield Structure
88     //
89     union tVIF_STAT {
90     struct {
91     u32 VPS : 2; // Vif(0/1) status; 00 - idle, 01 - waiting for data following vifcode, 10 - decoding vifcode, 11 - decompressing/trasferring data follwing vifcode.
92     u32 VEW : 1; // E-bit wait (1 - wait, 0 - don't wait)
93     u32 VGW : 1; // Status waiting for the end of gif transfer (Vif1 only)
94 william 62 u32 _reserved : 2;
95 william 31 u32 MRK : 1; // Mark Detect
96     u32 DBF : 1; // Double Buffer Flag
97     u32 VSS : 1; // Stopped by STOP
98     u32 VFS : 1; // Stopped by ForceBreak
99     u32 VIS : 1; // Vif Interrupt Stall
100     u32 INT : 1; // Intereupt by the i bit.
101     u32 ER0 : 1; // DmaTag Mismatch error.
102     u32 ER1 : 1; // VifCode error
103 william 62 u32 _reserved2 : 9;
104 william 31 u32 FDR : 1; // VIF/FIFO transfer direction. (false - memory -> Vif, true - Vif -> memory)
105     u32 FQC : 5; // Amount of data. Up to 8 qwords on Vif0, 16 on Vif1.
106     };
107     u32 _u32;
108    
109     tVIF_STAT(u32 val) { _u32 = val; }
110     bool test(u32 flags) const { return !!(_u32 & flags); }
111     void set_flags (u32 flags) { _u32 |= flags; }
112     void clear_flags(u32 flags) { _u32 &= ~flags; }
113     void reset() { _u32 = 0; }
114     wxString desc() const { return wxsFormat(L"Stat: 0x%x", _u32); }
115     };
116    
117     #define VIF_STAT(value) ((tVIF_STAT)(value))
118    
119     union tVIF_FBRST {
120     struct {
121     u32 RST : 1; // Resets Vif(0/1) when written.
122     u32 FBK : 1; // Causes a Forcebreak to Vif((0/1) when true. (Stall)
123     u32 STP : 1; // Stops after the end of the Vifcode in progress when true. (Stall)
124     u32 STC : 1; // Cancels the Vif(0/1) stall and clears Vif Stats VSS, VFS, VIS, INT, ER0 & ER1.
125 william 62 u32 _reserved : 28;
126 william 31 };
127     u32 _u32;
128    
129     tVIF_FBRST(u32 val) { _u32 = val; }
130     bool test (u32 flags) const { return !!(_u32 & flags); }
131     void set_flags (u32 flags) { _u32 |= flags; }
132     void clear_flags(u32 flags) { _u32 &= ~flags; }
133     void reset() { _u32 = 0; }
134     wxString desc() const { return wxsFormat(L"Fbrst: 0x%x", _u32); }
135     };
136    
137     #define FBRST(value) ((tVIF_FBRST)(value))
138    
139     union tVIF_ERR {
140     struct {
141     u32 MII : 1; // Masks Stat INT.
142     u32 ME0 : 1; // Masks Stat Err0.
143     u32 ME1 : 1; // Masks Stat Err1.
144 william 62 u32 _reserved : 29;
145 william 31 };
146     u32 _u32;
147    
148     tVIF_ERR (u32 val) { _u32 = val; }
149     void write(u32 val) { _u32 = val; }
150     bool test (u32 flags) const { return !!(_u32 & flags); }
151     void set_flags (u32 flags) { _u32 |= flags; }
152     void clear_flags(u32 flags) { _u32 &= ~flags; }
153     void reset() { _u32 = 0; }
154     wxString desc() const { return wxsFormat(L"Err: 0x%x", _u32); }
155     };
156    
157     struct vifCycle
158     {
159     u8 cl, wl;
160     u8 pad[2];
161     };
162    
163     struct VIFregisters {
164     tVIF_STAT stat;
165 william 62 u32 _pad0[3];
166 william 31 u32 fbrst;
167 william 62 u32 _pad1[3];
168 william 31 tVIF_ERR err;
169 william 62 u32 _pad2[3];
170 william 31 u32 mark;
171 william 62 u32 _pad3[3];
172 william 31 vifCycle cycle; //data write cycle
173 william 62 u32 _pad4[3];
174 william 31 u32 mode;
175 william 62 u32 _pad5[3];
176 william 31 u32 num;
177 william 62 u32 _pad6[3];
178 william 31 u32 mask;
179 william 62 u32 _pad7[3];
180 william 31 u32 code;
181 william 62 u32 _pad8[3];
182 william 31 u32 itops;
183 william 62 u32 _pad9[3];
184 william 31 u32 base; // Not used in VIF0
185 william 62 u32 _pad10[3];
186 william 31 u32 ofst; // Not used in VIF0
187 william 62 u32 _pad11[3];
188 william 31 u32 tops; // Not used in VIF0
189 william 62 u32 _pad12[3];
190 william 31 u32 itop;
191 william 62 u32 _pad13[3];
192 william 31 u32 top; // Not used in VIF0
193 william 62 u32 _pad14[3];
194 william 31 u32 mskpath3;
195 william 62 u32 _pad15[3];
196 william 31 u32 r0; // row0 register
197 william 62 u32 _pad16[3];
198 william 31 u32 r1; // row1 register
199 william 62 u32 _pad17[3];
200 william 31 u32 r2; // row2 register
201 william 62 u32 _pad18[3];
202 william 31 u32 r3; // row3 register
203 william 62 u32 _pad19[3];
204 william 31 u32 c0; // col0 register
205 william 62 u32 _pad20[3];
206 william 31 u32 c1; // col1 register
207 william 62 u32 _pad21[3];
208 william 31 u32 c2; // col2 register
209 william 62 u32 _pad22[3];
210 william 31 u32 c3; // col3 register
211 william 62 u32 _pad23[3];
212 william 31 u32 offset; // internal UNPACK offset
213     u32 addr;
214     };
215    
216 william 62 static VIFregisters& vif0Regs = (VIFregisters&)eeHw[0x3800];
217     static VIFregisters& vif1Regs = (VIFregisters&)eeHw[0x3C00];
218 william 31
219     #define _vifT template <int idx>
220 william 62 #define GetVifX (idx ? (vif1) : (vif0))
221 william 31 #define vifXch (idx ? (vif1ch) : (vif0ch))
222     #define vifXRegs (idx ? (vif1Regs) : (vif0Regs))
223    
224     extern void dmaVIF0();
225     extern void dmaVIF1();
226     extern void mfifoVIF1transfer(int qwc);
227 william 273 extern bool VIF0transfer(u32 *data, int size, bool TTE=0);
228     extern bool VIF1transfer(u32 *data, int size, bool TTE=0);
229 william 31 extern void vifMFIFOInterrupt();
230 william 62 extern bool CheckPath2GIF(EE_EventType channel);

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