/[pcsx2_0.9.7]/trunk/pcsx2/Sif0.cpp
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Diff of /trunk/pcsx2/Sif0.cpp

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--- trunk/pcsx2/Sif0.cpp	2010/09/07 03:24:11	31
+++ trunk/pcsx2/Sif0.cpp	2010/09/07 11:08:22	62
@@ -24,7 +24,7 @@
 
 static bool done = false;
 
-static __forceinline void Sif0Init()
+static __fi void Sif0Init()
 {
 	SIF_LOG("SIF0 DMA start...");
 	done = false;
@@ -33,16 +33,16 @@
 }
 
 // Write from Fifo to EE.
-static __forceinline bool WriteFifoToEE()
+static __fi bool WriteFifoToEE()
 {
-	const int readSize = min((s32)sif0dma->qwc, sif0.fifo.size >> 2);
+	const int readSize = min((s32)sif0dma.qwc, sif0.fifo.size >> 2);
 
 	tDMA_TAG *ptag;
 
-	//SIF_LOG(" EE SIF doing transfer %04Xqw to %08X", readSize, sif0dma->madr);
-	SIF_LOG("Write Fifo to EE: ----------- %lX of %lX", readSize << 2, sif0dma->qwc << 2);
+	//SIF_LOG(" EE SIF doing transfer %04Xqw to %08X", readSize, sif0dma.madr);
+	SIF_LOG("Write Fifo to EE: ----------- %lX of %lX", readSize << 2, sif0dma.qwc << 2);
 
-	ptag = sif0dma->getAddr(sif0dma->madr, DMAC_SIF0, true);
+	ptag = sif0dma.getAddr(sif0dma.madr, DMAC_SIF0, true);
 	if (ptag == NULL)
 	{
 		DevCon.Warning("Write Fifo to EE: ptag == NULL");
@@ -52,17 +52,17 @@
 	sif0.fifo.read((u32*)ptag, readSize << 2);
 
 	// Clearing handled by vtlb memory protection and manual blocks.
-	//Cpu->Clear(sif0dma->madr, readSize*4);
+	//Cpu->Clear(sif0dma.madr, readSize*4);
 
-	sif0dma->madr += readSize << 4;
+	sif0dma.madr += readSize << 4;
 	sif0.ee.cycles += readSize;	// fixme : BIAS is factored in above
-	sif0dma->qwc -= readSize;
+	sif0dma.qwc -= readSize;
 
 	return true;
 }
 
 // Write IOP to Fifo.
-static __forceinline bool WriteIOPtoFifo()
+static __fi bool WriteIOPtoFifo()
 {
 	// There's some data ready to transfer into the fifo..
 	const int writeSize = min(sif0.iop.counter, sif0.fifo.free());
@@ -73,28 +73,28 @@
 	hw_dma(9).madr += writeSize << 2;
 
 	// iop is 1/8th the clock rate of the EE and psxcycles is in words (not quadwords).
-	sif0.iop.cycles += (writeSize >> 2) * BIAS;		// fixme : should be >> 4
+	sif0.iop.cycles += (writeSize >> 2)/* * BIAS*/;		// fixme : should be >> 4
 	sif0.iop.counter -= writeSize;
 
 	return true;
 }
 
 // Read Fifo into an ee tag, transfer it to sif0dma, and process it.
-static __forceinline bool ProcessEETag()
+static __fi bool ProcessEETag()
 {
 	static __aligned16 u32 tag[4];
 
 	sif0.fifo.read((u32*)&tag[0], 4); // Tag
 	SIF_LOG("SIF0 EE read tag: %x %x %x %x", tag[0], tag[1], tag[2], tag[3]);
 
-	sif0dma->unsafeTransfer(((tDMA_TAG*)(tag)));
-	sif0dma->madr = tag[1];
+	sif0dma.unsafeTransfer(((tDMA_TAG*)(tag)));
+	sif0dma.madr = tag[1];
 	tDMA_TAG ptag(tag[0]);
 
 	SIF_LOG("SIF0 EE dest chain tag madr:%08X qwc:%04X id:%X irq:%d(%08X_%08X)",
-		sif0dma->madr, sif0dma->qwc, ptag.ID, ptag.IRQ, tag[1], tag[0]);
+		sif0dma.madr, sif0dma.qwc, ptag.ID, ptag.IRQ, tag[1], tag[0]);
 
-	if (sif0dma->chcr.TIE && ptag.IRQ)
+	if (sif0dma.chcr.TIE && ptag.IRQ)
 	{
 		//Console.WriteLn("SIF0 TIE");
 		sif0.ee.end = true;
@@ -104,13 +104,13 @@
 	{
 		case TAG_REFE:
 			sif0.ee.end = true;
-			if (dmacRegs->ctrl.STS != NO_STS)
-				dmacRegs->stadr.ADDR = sif0dma->madr + (sif0dma->qwc * 16);
+			if (dmacRegs.ctrl.STS != NO_STS)
+				dmacRegs.stadr.ADDR = sif0dma.madr + (sif0dma.qwc * 16);
 				break;
 
 		case TAG_REFS:
-			if (dmacRegs->ctrl.STS != NO_STS)
-				dmacRegs->stadr.ADDR = sif0dma->madr + (sif0dma->qwc * 16);
+			if (dmacRegs.ctrl.STS != NO_STS)
+				dmacRegs.stadr.ADDR = sif0dma.madr + (sif0dma.qwc * 16);
 				break;
 
 		case TAG_END:
@@ -121,7 +121,7 @@
 }
 
 // Read Fifo into an iop tag, and transfer it to hw_dma(9). And presumably process it.
-static __forceinline bool ProcessIOPTag()
+static __fi bool ProcessIOPTag()
 {
 	// Process DMA tag at hw_dma(9).tadr
 	sif0.iop.data = *(sifData *)iopPhysMem(hw_dma(9).tadr);
@@ -141,7 +141,7 @@
 }
 
 // Stop transferring ee, and signal an interrupt.
-static __forceinline void EndEE()
+static __fi void EndEE()
 {
 	SIF_LOG("Sif0: End EE");
 	sif0.ee.end = false;
@@ -156,7 +156,7 @@
 }
 
 // Stop transferring iop, and signal an interrupt.
-static __forceinline void EndIOP()
+static __fi void EndIOP()
 {
 	SIF_LOG("Sif0: End IOP");
 	sif0data = 0;
@@ -175,9 +175,9 @@
 }
 
 // Handle the EE transfer.
-static __forceinline void HandleEETransfer()
+static __fi void HandleEETransfer()
 {
-	if(sif0dma->chcr.STR == false)
+	if(sif0dma.chcr.STR == false)
 	{
 		DevCon.Warning("Replacement for irq prevention hack EE SIF0");
 		sif0.ee.end = false;
@@ -185,22 +185,22 @@
 		return;
 	}
 
-	if (dmacRegs->ctrl.STS == STS_SIF0)
+	if (dmacRegs.ctrl.STS == STS_SIF0)
 	{
 		DevCon.Warning("SIF0 stall control");
 	}
 
-	/*if (sif0dma->qwc == 0)
-		if (sif0dma->chcr.MOD == NORMAL_MODE)
+	/*if (sif0dma.qwc == 0)
+		if (sif0dma.chcr.MOD == NORMAL_MODE)
 			if (!sif0.ee.end){
 				DevCon.Warning("sif0 irq prevented");
 				done = true;
 				return;
 			}*/
 
-	if (sif0dma->qwc <= 0)
+	if (sif0dma.qwc <= 0)
 	{
-		if ((sif0dma->chcr.MOD == NORMAL_MODE) || sif0.ee.end)
+		if ((sif0dma.chcr.MOD == NORMAL_MODE) || sif0.ee.end)
 		{
 			// Stop transferring ee, and signal an interrupt.
 			done = true;
@@ -214,7 +214,7 @@
 		}
 	}
 
-	if (sif0dma->qwc > 0) // If we're writing something, continue to do so.
+	if (sif0dma.qwc > 0) // If we're writing something, continue to do so.
 	{
 		// Write from Fifo to EE.
 		if (sif0.fifo.size > 0)
@@ -253,7 +253,7 @@
 // SIF - 8 = 0 (pos=12)
 // SIF0 DMA end...
 
-static __forceinline void HandleIOPTransfer()
+static __fi void HandleIOPTransfer()
 {
 	if (sif0.iop.counter <= 0) // If there's no more to transfer
 	{
@@ -280,13 +280,13 @@
 	}
 }
 
-static __forceinline void Sif0End()
+static __fi void Sif0End()
 {
 	SIF_LOG("SIF0 DMA end...");
 }
 
 // Transfer IOP to EE, putting data in the fifo as an intermediate step.
-__forceinline void SIF0Dma()
+__fi void SIF0Dma()
 {
 	int BusyCheck = 0;
 	Sif0Init();
@@ -298,51 +298,61 @@
 
 		if (sif0.iop.busy)
 		{
-			if(sif0.fifo.free() > 0) BusyCheck++;
-			HandleIOPTransfer();
+			if(sif0.fifo.free() > 0 || (sif0.iop.end == true && sif0.iop.counter == 0)) 
+			{
+				BusyCheck++;
+				HandleIOPTransfer();
+			}
 		}
 		if (sif0.ee.busy)
 		{
-			if(sif0.fifo.size >= 4) BusyCheck++;
-			HandleEETransfer();
+			if(sif0.fifo.size >= 4 || (sif0.ee.end == true && sif0dma.qwc == 0)) 
+			{
+				BusyCheck++;
+				HandleEETransfer();
+			}
 		}
-	} while (!done && BusyCheck > 0); // Substituting (sif0.ee.busy || sif0.iop.busy) breaks things.
+	} while (/*!done && */BusyCheck > 0); // Substituting (sif0.ee.busy || sif0.iop.busy) breaks things.
 
 	Sif0End();
 }
 
-__forceinline void  sif0Interrupt()
+__fi void  sif0Interrupt()
 {
 	HW_DMA9_CHCR &= ~0x01000000;
 	psxDmaInterrupt2(2);
 }
 
-__forceinline void  EEsif0Interrupt()
+__fi void  EEsif0Interrupt()
 {
 	hwDmacIrq(DMAC_SIF0);
-	sif0dma->chcr.STR = false;
+	sif0dma.chcr.STR = false;
 }
 
-__forceinline void dmaSIF0()
+__fi void dmaSIF0()
 {
-	SIF_LOG(wxString(L"dmaSIF0" + sif0dma->cmqt_to_str()).To8BitData());
+	SIF_LOG(wxString(L"dmaSIF0" + sif0dma.cmqt_to_str()).To8BitData());
 
 	if (sif0.fifo.readPos != sif0.fifo.writePos)
 	{
 		SIF_LOG("warning, sif0.fifoReadPos != sif0.fifoWritePos");
 	}
 
-	if(sif0dma->chcr.MOD == CHAIN_MODE && sif0dma->qwc > 0) DevCon.Warning(L"SIF0 QWC on Chain CHCR " + sif0dma->chcr.desc());
+	//if(sif0dma.chcr.MOD == CHAIN_MODE && sif0dma.qwc > 0) DevCon.Warning(L"SIF0 QWC on Chain CHCR " + sif0dma.chcr.desc());
 	psHu32(SBUS_F240) |= 0x2000;
 	sif0.ee.busy = true;
 
+	// Okay, this here is needed currently (r3644). 
+	// FFX battles in the thunder plains map die otherwise, Phantasy Star 4 as well
+	// These 2 games could be made playable again by increasing the time the EE or the IOP run,
+	// showing that this is very timing sensible.
+	// Doing this DMA unfortunately brings back an old warning in Legend of Legaia though, but it still works.
 	if (sif0.iop.busy)
 	{
-        XMMRegisters::Freeze();
-		hwIntcIrq(INTC_SBUS);
+        //hwIntcIrq(INTC_SBUS); // not sure, so let's not
 		SIF0Dma();
-		psHu32(SBUS_F240) &= ~0x20;
-		psHu32(SBUS_F240) &= ~0x2000;
-        XMMRegisters::Thaw();
+		// Do we really want to mess with the SIF flags like that? Nah.
+		//psHu32(SBUS_F240) &= ~0x20;
+		//psHu32(SBUS_F240) &= ~0x2000;
 	}
 }

 

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