/[pcsx2_0.9.7]/trunk/pcsx2/R5900.h
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Annotation of /trunk/pcsx2/R5900.h

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1 william 31 /* PCSX2 - PS2 Emulator for PCs
2     * Copyright (C) 2002-2010 PCSX2 Dev Team
3     *
4     * PCSX2 is free software: you can redistribute it and/or modify it under the terms
5     * of the GNU Lesser General Public License as published by the Free Software Found-
6     * ation, either version 3 of the License, or (at your option) any later version.
7     *
8     * PCSX2 is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
9     * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
10     * PURPOSE. See the GNU General Public License for more details.
11     *
12     * You should have received a copy of the GNU General Public License along with PCSX2.
13     * If not, see <http://www.gnu.org/licenses/>.
14     */
15    
16     #pragma once
17    
18 william 62 class BaseR5900Exception;
19 william 31
20 william 62 // --------------------------------------------------------------------------------------
21     // Recompiler Stuffs
22     // --------------------------------------------------------------------------------------
23 william 31 // This code section contains recompiler vars that are used in "shared" code. Placing
24     // them in iR5900.h would mean having to include that into more files than I care to
25     // right now, so we're sticking them here for now until a better solution comes along.
26    
27     extern bool g_SkipBiosHack;
28     extern bool g_GameStarted;
29    
30     namespace Exception
31     {
32     // Implementation Note: this exception has no meaningful type information and we don't
33     // care to have it be caught by any BaseException handlers lying about, so let's not
34     // derive from BaseException :D
35     class ExitCpuExecute
36     {
37     public:
38     explicit ExitCpuExecute() { }
39     };
40     }
41    
42 william 62 // --------------------------------------------------------------------------------------
43     // EE Bios function name tables.
44     // --------------------------------------------------------------------------------------
45 william 31 namespace R5900 {
46     extern const char* const bios[256];
47     }
48    
49     extern s32 EEsCycle;
50     extern u32 EEoCycle;
51    
52     union GPR_reg { // Declare union type GPR register
53 william 62 u128 UQ;
54     s128 SQ;
55 william 31 u64 UD[2]; //128 bits
56     s64 SD[2];
57     u32 UL[4];
58     s32 SL[4];
59     u16 US[8];
60     s16 SS[8];
61     u8 UC[16];
62     s8 SC[16];
63     };
64    
65     union GPRregs {
66     struct {
67     GPR_reg r0, at, v0, v1, a0, a1, a2, a3,
68     t0, t1, t2, t3, t4, t5, t6, t7,
69     s0, s1, s2, s3, s4, s5, s6, s7,
70     t8, t9, k0, k1, gp, sp, s8, ra;
71     } n;
72     GPR_reg r[32];
73     };
74    
75     union PERFregs {
76     struct
77     {
78     union
79     {
80     struct
81     {
82     u32 pad0:1; // LSB should always be zero (or undefined)
83     u32 EXL0:1; // enable PCR0 during Level 1 exception handling
84     u32 K0:1; // enable PCR0 during Kernel Mode execution
85     u32 S0:1; // enable PCR0 during Supervisor mode execution
86     u32 U0:1; // enable PCR0 during User-mode execution
87     u32 Event0:5; // PCR0 event counter (all values except 1 ignored at this time)
88    
89     u32 pad1:1; // more zero/undefined padding [bit 10]
90    
91     u32 EXL1:1; // enable PCR1 during Level 1 exception handling
92     u32 K1:1; // enable PCR1 during Kernel Mode execution
93     u32 S1:1; // enable PCR1 during Supervisor mode execution
94     u32 U1:1; // enable PCR1 during User-mode execution
95     u32 Event1:5; // PCR1 event counter (all values except 1 ignored at this time)
96    
97     u32 Reserved:11;
98     u32 CTE:1; // Counter enable bit, no counting if set to zero.
99     } b;
100    
101     u32 val;
102     } pccr;
103    
104     u32 pcr0, pcr1, pad;
105     } n;
106     u32 r[4];
107     };
108    
109     union CP0regs {
110     struct {
111     u32 Index, Random, EntryLo0, EntryLo1,
112     Context, PageMask, Wired, Reserved0,
113     BadVAddr, Count, EntryHi, Compare;
114     union {
115     struct {
116     u32 IE:1; // Bit 0: Interrupt Enable flag.
117     u32 EXL:1; // Bit 1: Exception Level, set on any exception not covered by ERL.
118     u32 ERL:1; // Bit 2: Error level, set on Resetm NMI, perf/debug exceptions.
119     u32 KSU:2; // Bits 3-4: Kernel [clear] / Supervisor [set] mode
120     u32 unused0:3;
121     u32 IM:8; // Bits 10-15: Interrupt mask (bits 12,13,14 are unused)
122     u32 EIE:1; // Bit 16: IE bit enabler. When cleared, ints are disabled regardless of IE status.
123     u32 _EDI:1; // Bit 17: Interrupt Enable (set enables ints in all modes, clear enables ints in kernel mode only)
124     u32 CH:1; // Bit 18: Status of most recent cache instruction (set for hit, clear for miss)
125     u32 unused1:3;
126     u32 BEV:1; // Bit 22: if set, use bootstrap for TLB/general exceptions
127     u32 DEV:1; // Bit 23: if set, use bootstrap for perf/debug exceptions
128     u32 unused2:2;
129     u32 FR:1; // (?)
130     u32 unused3:1;
131     u32 CU:4; // Bits 28-31: Co-processor Usable flag
132     } b;
133     u32 val;
134     } Status;
135     u32 Cause, EPC, PRid,
136     Config, LLAddr, WatchLO, WatchHI,
137     XContext, Reserved1, Reserved2, Debug,
138     DEPC, PerfCnt, ErrCtl, CacheErr,
139     TagLo, TagHi, ErrorEPC, DESAVE;
140     } n;
141     u32 r[32];
142     };
143    
144     struct cpuRegisters {
145     GPRregs GPR; // GPR regs
146     // NOTE: don't change order since recompiler uses it
147     GPR_reg HI;
148     GPR_reg LO; // hi & log 128bit wide
149     CP0regs CP0; // is COP0 32bit?
150     u32 sa; // shift amount (32bit), needs to be 16 byte aligned
151     u32 IsDelaySlot; // set true when the current instruction is a delay slot.
152     u32 pc; // Program counter, when changing offset in struct, check iR5900-X.S to make sure offset is correct
153     u32 code; // current instruction
154     PERFregs PERF;
155     u32 eCycle[32];
156     u32 sCycle[32]; // for internal counters
157     u32 cycle; // calculate cpucycles..
158     u32 interrupt;
159     int branch;
160     int opmode; // operating mode
161     u32 tempcycles;
162     };
163    
164     // used for optimization
165     union GPR_reg64 {
166     u64 UD[1]; //64 bits
167     s64 SD[1];
168     u32 UL[2];
169     s32 SL[3];
170     u16 US[4];
171     s16 SS[4];
172     u8 UC[8];
173     s8 SC[8];
174     };
175    
176     union FPRreg {
177     float f;
178     u32 UL;
179     s32 SL; // signed 32bit used for sign extension in interpreters.
180     };
181    
182     struct fpuRegisters {
183     FPRreg fpr[32]; // 32bit floating point registers
184     u32 fprc[32]; // 32bit floating point control registers
185     FPRreg ACC; // 32 bit accumulator
186     u32 ACCflag; // an internal accumulator overflow flag
187     };
188    
189     struct tlbs
190     {
191     u32 PageMask,EntryHi;
192     u32 EntryLo0,EntryLo1;
193     u32 Mask, nMask;
194     u32 G;
195     u32 ASID;
196     u32 VPN2;
197     u32 PFN0;
198     u32 PFN1;
199     u32 S;
200     };
201    
202     #ifndef _PC_
203    
204     /*#define _i64(x) (s64)x
205     #define _u64(x) (u64)x
206    
207     #define _i32(x) (s32)x
208     #define _u32(x) (u32)x
209    
210     #define _i16(x) (s16)x
211     #define _u16(x) (u16)x
212    
213     #define _i8(x) (s8)x
214     #define _u8(x) (u8)x*/
215    
216     ////////////////////////////////////////////////////////////////////
217     // R5900 Instruction Macros
218    
219     #define _PC_ cpuRegs.pc // The next PC to be executed - only used in this header and R3000A.h
220    
221     #define _Funct_ ((cpuRegs.code ) & 0x3F) // The funct part of the instruction register
222     #define _Rd_ ((cpuRegs.code >> 11) & 0x1F) // The rd part of the instruction register
223     #define _Rt_ ((cpuRegs.code >> 16) & 0x1F) // The rt part of the instruction register
224     #define _Rs_ ((cpuRegs.code >> 21) & 0x1F) // The rs part of the instruction register
225     #define _Sa_ ((cpuRegs.code >> 6) & 0x1F) // The sa part of the instruction register
226     #define _Im_ ((u16)cpuRegs.code) // The immediate part of the instruction register
227     #define _Target_ (cpuRegs.code & 0x03ffffff) // The target part of the instruction register
228    
229     #define _Imm_ ((s16)cpuRegs.code) // sign-extended immediate
230     #define _ImmU_ (cpuRegs.code&0xffff) // zero-extended immediate
231     #define _ImmSB_ (cpuRegs.code&0x8000) // gets the sign-bit of the immediate value
232    
233     #define _Opcode_ (cpuRegs.code >> 26 )
234    
235     #define _JumpTarget_ ((_Target_ << 2) + (_PC_ & 0xf0000000)) // Calculates the target during a jump instruction
236     #define _BranchTarget_ (((s32)(s16)_Im_ * 4) + _PC_) // Calculates the target during a branch instruction
237     #define _TrapCode_ ((u16)cpuRegs.code >> 6) // error code for non-immediate trap instructions.
238    
239     #define _SetLink(x) (cpuRegs.GPR.r[x].UD[0] = _PC_ + 4) // Sets the return address in the link register
240    
241     #endif
242    
243     extern __aligned16 cpuRegisters cpuRegs;
244     extern __aligned16 fpuRegisters fpuRegs;
245     extern __aligned16 tlbs tlb[48];
246    
247 william 62 extern u32 g_nextEventCycle;
248 william 31 extern bool eeEventTestIsActive;
249     extern u32 s_iLastCOP0Cycle;
250     extern u32 s_iLastPERFCycle[2];
251    
252     void intSetBranch();
253    
254     // This is a special form of the interpreter's doBranch that is run from various
255     // parts of the Recs (namely COP0's branch codes and stuff).
256     void __fastcall intDoBranch(u32 target);
257    
258     // modules loaded at hardcoded addresses by the kernel
259 william 62 const u32 EEKERNEL_START = 0;
260     const u32 EENULL_START = 0x81FC0;
261     const u32 EELOAD_START = 0x82000;
262     const u32 EELOAD_SIZE = 0x20000; // overestimate for searching
263 william 31
264 william 62 extern void __fastcall eeGameStarting();
265     extern void __fastcall eeloadReplaceOSDSYS();
266 william 31
267 william 62 // --------------------------------------------------------------------------------------
268     // R5900cpu
269     // --------------------------------------------------------------------------------------
270 william 31 // [TODO] : This is on the list to get converted to a proper C++ class. I'm putting it
271     // off until I get my new IOPint and IOPrec re-merged. --air
272     //
273     struct R5900cpu
274     {
275     // Memory allocation function, for allocating virtual memory spaces needed by
276 william 280 // the virtual cpu provider. Allocating additional heap memory from this method is
277     // NOT recommended. Heap allocations should be performed by Reset only. This
278     // maximizes the likeliness of reservations claiming addresses they prefer.
279     //
280 william 31 // Thread Affinity:
281 william 280 // Called from the main/UI thread only. Cpu execution status is guaranteed to
282     // be inactive. No locking is necessary.
283 william 31 //
284 william 62 // Exception Throws:
285 william 280 // HardwareDeficiency - The host machine's hardware does not support this CPU provider.
286 william 31 // OutOfMemory - Not enough memory, or the memory areas required were already
287     // reserved.
288 william 280 void (*Reserve)();
289 william 31
290 william 280 // Deallocates ram allocated by Allocate, Reserve, and/or by runtime code execution.
291 william 31 //
292     // Thread Affinity:
293 william 280 // Called from the main/UI thread only. Cpu execution status is guaranteed to
294     // be inactive. No locking is necessary.
295 william 31 //
296     // Exception Throws: None. This function is a destructor, and should not throw.
297     //
298     void (*Shutdown)();
299    
300     // Initializes / Resets code execution states. Typically implementation is only
301     // needed for recompilers, as interpreters have no internal execution states and
302     // rely on the CPU/VM states almost entirely.
303     //
304     // Thread Affinity:
305 william 280 // Can be called from any thread. CPU execution status is indeterminate and may
306     // already be in progress. Implementations should be sure to queue and execute
307     // resets at the earliest safe convenience (typically right before recompiling a
308     // new block of code, or after a vsync event).
309 william 31 //
310 william 62 // Exception Throws: Emulator-defined. Common exception types to expect are
311 william 31 // OutOfMemory, Stream Exceptions
312     //
313     void (*Reset)();
314    
315     // Steps a single instruction. Meant to be used by debuggers. Is currently unused
316     // and unimplemented. Future note: recompiler "step" should *always* fall back
317     // on interpreters.
318     //
319     // Exception Throws: [TODO] (possible execution-related throws to be added)
320     //
321     void (*Step)();
322    
323     // Executes code until a break is signaled. Execution can be paused or suspended
324     // via thread-style signals that are handled by CheckExecutionState callbacks.
325     // Execution Breakages are handled the same way, where-by a signal causes the Execute
326     // call to return at the nearest state check (typically handled internally using
327     // either C++ exceptions or setjmp/longjmp).
328     //
329 william 62 // Exception Throws:
330     // Throws BaseR5900Exception and all derivatives.
331     // Throws FileNotFound or other Streaming errors (typically related to BIOS MEC/NVM)
332 william 31 //
333     void (*Execute)();
334    
335     // Checks for execution suspension or cancellation. In pthreads terms this provides
336     // a "cancellation point." Execution state checks are typically performed at Vsyncs
337     // by the generic VM event handlers in R5900.cpp/Counters.cpp (applies to both recs
338     // and ints).
339     //
340     // Implementation note: Because of the nuances of recompiled code execution, setjmp
341     // may be used in place of thread cancellation or C++ exceptions (non-SEH exceptions
342 william 62 // cannot unwind through the recompiled code stackframes, thus longjmp must be used).
343 william 31 //
344     // Thread Affinity:
345 william 62 // Must be called on the same thread as Execute.
346 william 31 //
347     // Exception Throws:
348 william 62 // May throw Execution/Pthreads cancellations if the compiler supports SEH.
349 william 31 //
350     void (*CheckExecutionState)();
351    
352 william 62 // Safely throws host exceptions from executing code (either recompiled or interpreted).
353     // If this function is called outside the context of the CPU's code execution, then the
354     // given exception will be re-thrown automatically.
355     //
356     // Exception Throws:
357     // (SEH) Rethrows the given exception immediately.
358     // (setjmp) Re-throws immediately if called from outside the context of dynamically
359     // generated code (either non-executing contexts or interpreters). Does not throw
360     // otherwise.
361     //
362     void (*ThrowException)( const BaseException& ex );
363     void (*ThrowCpuException)( const BaseR5900Exception& ex );
364    
365 william 31 // Manual recompiled code cache clear; typically useful to recompilers only. Size is
366     // in MIPS words (32 bits). Dev note: this callback is nearly obsolete, and might be
367     // better off replaced with some generic API callbacks from VTLB block protection.
368     // Also: the calls from COP0's TLB remap code should be replaced with full recompiler
369     // resets, since TLB remaps affect more than just the code they contain (code that
370 william 280 // may reference the remapped blocks via memory loads/stores, for example).
371 william 31 //
372     // Thread Affinity Rule:
373     // Can be called from any thread (namely for being called from debugging threads)
374     //
375     // Exception Throws: [TODO] Emulator defined? (probably shouldn't throw, probably
376     // doesn't matter if we're stripping it out soon. ;)
377     //
378     void (*Clear)(u32 Addr, u32 Size);
379 william 280
380     uint (*GetCacheReserve)();
381     void (*SetCacheReserve)( uint reserveInMegs );
382 william 31 };
383    
384     extern R5900cpu *Cpu;
385     extern R5900cpu intCpu;
386     extern R5900cpu recCpu;
387    
388 william 62 enum EE_EventType
389     {
390     DMAC_VIF0 = 0,
391     DMAC_VIF1,
392     DMAC_GIF,
393     DMAC_FROM_IPU,
394     DMAC_TO_IPU,
395     DMAC_SIF0,
396     DMAC_SIF1,
397     DMAC_SIF2,
398     DMAC_FROM_SPR,
399     DMAC_TO_SPR,
400    
401     DMAC_MFIFO_VIF,
402     DMAC_MFIFO_GIF,
403    
404     // We're setting error conditions through hwDmacIrq, so these correspond to the conditions above.
405     DMAC_STALL_SIS = 13, // SIS
406     DMAC_MFIFO_EMPTY = 14, // MEIS
407     DMAC_BUS_ERROR = 15 // BEIS
408     };
409    
410     extern void CPU_INT( EE_EventType n, s32 ecycle );
411     extern uint intcInterrupt();
412     extern uint dmacInterrupt();
413    
414    
415 william 31 extern void cpuInit();
416     extern void cpuReset(); // can throw Exception::FileNotFound.
417     extern void cpuException(u32 code, u32 bd);
418     extern void cpuTlbMissR(u32 addr, u32 bd);
419     extern void cpuTlbMissW(u32 addr, u32 bd);
420     extern void cpuTestHwInts();
421     extern void cpuClearInt(uint n);
422    
423 william 62 extern void cpuSetNextEvent( u32 startCycle, s32 delta );
424     extern void cpuSetNextEventDelta( s32 delta );
425 william 31 extern int cpuTestCycle( u32 startCycle, s32 delta );
426 william 62 extern void cpuSetEvent();
427 william 31
428 william 62 extern void _cpuEventTest_Shared(); // for internal use by the Dynarecs and Ints inside R5900:
429 william 31
430     extern void cpuTestINTCInts();
431     extern void cpuTestDMACInts();
432     extern void cpuTestTIMRInts();
433    
434     ////////////////////////////////////////////////////////////////////
435     // Exception Codes
436    
437     #define EXC_CODE(x) ((x)<<2)
438    
439     #define EXC_CODE_Int EXC_CODE(0)
440     #define EXC_CODE_Mod EXC_CODE(1) /* TLB Modification exception */
441     #define EXC_CODE_TLBL EXC_CODE(2) /* TLB Miss exception (load or instruction fetch) */
442     #define EXC_CODE_TLBS EXC_CODE(3) /* TLB Miss exception (store) */
443     #define EXC_CODE_AdEL EXC_CODE(4)
444     #define EXC_CODE_AdES EXC_CODE(5)
445     #define EXC_CODE_IBE EXC_CODE(6)
446     #define EXC_CODE_DBE EXC_CODE(7)
447     #define EXC_CODE_Sys EXC_CODE(8)
448     #define EXC_CODE_Bp EXC_CODE(9)
449     #define EXC_CODE_Ri EXC_CODE(10)
450     #define EXC_CODE_CpU EXC_CODE(11)
451     #define EXC_CODE_Ov EXC_CODE(12)
452     #define EXC_CODE_Tr EXC_CODE(13)
453     #define EXC_CODE_FPE EXC_CODE(15)
454     #define EXC_CODE_WATCH EXC_CODE(23)
455     #define EXC_CODE__MASK 0x0000007c
456     #define EXC_CODE__SHIFT 2

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