/[pcsx2_0.9.7]/trunk/pcsx2/R5900.h
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Annotation of /trunk/pcsx2/R5900.h

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Tue Sep 7 03:24:11 2010 UTC (9 years, 5 months ago) by william
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committing r3113 initial commit again...
1 william 31 /* PCSX2 - PS2 Emulator for PCs
2     * Copyright (C) 2002-2010 PCSX2 Dev Team
3     *
4     * PCSX2 is free software: you can redistribute it and/or modify it under the terms
5     * of the GNU Lesser General Public License as published by the Free Software Found-
6     * ation, either version 3 of the License, or (at your option) any later version.
7     *
8     * PCSX2 is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
9     * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
10     * PURPOSE. See the GNU General Public License for more details.
11     *
12     * You should have received a copy of the GNU General Public License along with PCSX2.
13     * If not, see <http://www.gnu.org/licenses/>.
14     */
15    
16     #pragma once
17    
18     //////////////////////////////////////////////////////////////////////////////////////////
19     #ifndef __LINUX__
20     #pragma region Recompiler Stuffs
21     #endif
22    
23     // This code section contains recompiler vars that are used in "shared" code. Placing
24     // them in iR5900.h would mean having to include that into more files than I care to
25     // right now, so we're sticking them here for now until a better solution comes along.
26    
27     extern bool g_EEFreezeRegs;
28     extern bool g_SkipBiosHack;
29     extern bool g_GameStarted;
30    
31     namespace Exception
32     {
33     // Implementation Note: this exception has no meaningful type information and we don't
34     // care to have it be caught by any BaseException handlers lying about, so let's not
35     // derive from BaseException :D
36     class ExitCpuExecute
37     {
38     public:
39     explicit ExitCpuExecute() { }
40     };
41     }
42     #ifndef __LINUX__
43     #pragma endregion
44     #endif
45    
46     //////////////////////////////////////////////////////////////////////////////////////////
47     // EE Bios function name tables.
48     namespace R5900 {
49     extern const char* const bios[256];
50     }
51    
52     extern s32 EEsCycle;
53     extern u32 EEoCycle;
54    
55     union GPR_reg { // Declare union type GPR register
56     u64 UD[2]; //128 bits
57     s64 SD[2];
58     u32 UL[4];
59     s32 SL[4];
60     u16 US[8];
61     s16 SS[8];
62     u8 UC[16];
63     s8 SC[16];
64     };
65    
66     union GPRregs {
67     struct {
68     GPR_reg r0, at, v0, v1, a0, a1, a2, a3,
69     t0, t1, t2, t3, t4, t5, t6, t7,
70     s0, s1, s2, s3, s4, s5, s6, s7,
71     t8, t9, k0, k1, gp, sp, s8, ra;
72     } n;
73     GPR_reg r[32];
74     };
75    
76     union PERFregs {
77     struct
78     {
79     union
80     {
81     struct
82     {
83     u32 pad0:1; // LSB should always be zero (or undefined)
84     u32 EXL0:1; // enable PCR0 during Level 1 exception handling
85     u32 K0:1; // enable PCR0 during Kernel Mode execution
86     u32 S0:1; // enable PCR0 during Supervisor mode execution
87     u32 U0:1; // enable PCR0 during User-mode execution
88     u32 Event0:5; // PCR0 event counter (all values except 1 ignored at this time)
89    
90     u32 pad1:1; // more zero/undefined padding [bit 10]
91    
92     u32 EXL1:1; // enable PCR1 during Level 1 exception handling
93     u32 K1:1; // enable PCR1 during Kernel Mode execution
94     u32 S1:1; // enable PCR1 during Supervisor mode execution
95     u32 U1:1; // enable PCR1 during User-mode execution
96     u32 Event1:5; // PCR1 event counter (all values except 1 ignored at this time)
97    
98     u32 Reserved:11;
99     u32 CTE:1; // Counter enable bit, no counting if set to zero.
100     } b;
101    
102     u32 val;
103     } pccr;
104    
105     u32 pcr0, pcr1, pad;
106     } n;
107     u32 r[4];
108     };
109    
110     union CP0regs {
111     struct {
112     u32 Index, Random, EntryLo0, EntryLo1,
113     Context, PageMask, Wired, Reserved0,
114     BadVAddr, Count, EntryHi, Compare;
115     union {
116     struct {
117     u32 IE:1; // Bit 0: Interrupt Enable flag.
118     u32 EXL:1; // Bit 1: Exception Level, set on any exception not covered by ERL.
119     u32 ERL:1; // Bit 2: Error level, set on Resetm NMI, perf/debug exceptions.
120     u32 KSU:2; // Bits 3-4: Kernel [clear] / Supervisor [set] mode
121     u32 unused0:3;
122     u32 IM:8; // Bits 10-15: Interrupt mask (bits 12,13,14 are unused)
123     u32 EIE:1; // Bit 16: IE bit enabler. When cleared, ints are disabled regardless of IE status.
124     u32 _EDI:1; // Bit 17: Interrupt Enable (set enables ints in all modes, clear enables ints in kernel mode only)
125     u32 CH:1; // Bit 18: Status of most recent cache instruction (set for hit, clear for miss)
126     u32 unused1:3;
127     u32 BEV:1; // Bit 22: if set, use bootstrap for TLB/general exceptions
128     u32 DEV:1; // Bit 23: if set, use bootstrap for perf/debug exceptions
129     u32 unused2:2;
130     u32 FR:1; // (?)
131     u32 unused3:1;
132     u32 CU:4; // Bits 28-31: Co-processor Usable flag
133     } b;
134     u32 val;
135     } Status;
136     u32 Cause, EPC, PRid,
137     Config, LLAddr, WatchLO, WatchHI,
138     XContext, Reserved1, Reserved2, Debug,
139     DEPC, PerfCnt, ErrCtl, CacheErr,
140     TagLo, TagHi, ErrorEPC, DESAVE;
141     } n;
142     u32 r[32];
143     };
144    
145     struct cpuRegisters {
146     GPRregs GPR; // GPR regs
147     // NOTE: don't change order since recompiler uses it
148     GPR_reg HI;
149     GPR_reg LO; // hi & log 128bit wide
150     CP0regs CP0; // is COP0 32bit?
151     u32 sa; // shift amount (32bit), needs to be 16 byte aligned
152     u32 IsDelaySlot; // set true when the current instruction is a delay slot.
153     u32 pc; // Program counter, when changing offset in struct, check iR5900-X.S to make sure offset is correct
154     u32 code; // current instruction
155     PERFregs PERF;
156     u32 eCycle[32];
157     u32 sCycle[32]; // for internal counters
158     u32 cycle; // calculate cpucycles..
159     u32 interrupt;
160     int branch;
161     int opmode; // operating mode
162     u32 tempcycles;
163     };
164    
165     // used for optimization
166     union GPR_reg64 {
167     u64 UD[1]; //64 bits
168     s64 SD[1];
169     u32 UL[2];
170     s32 SL[3];
171     u16 US[4];
172     s16 SS[4];
173     u8 UC[8];
174     s8 SC[8];
175     };
176    
177     union FPRreg {
178     float f;
179     u32 UL;
180     s32 SL; // signed 32bit used for sign extension in interpreters.
181     };
182    
183     struct fpuRegisters {
184     FPRreg fpr[32]; // 32bit floating point registers
185     u32 fprc[32]; // 32bit floating point control registers
186     FPRreg ACC; // 32 bit accumulator
187     u32 ACCflag; // an internal accumulator overflow flag
188     };
189    
190     struct tlbs
191     {
192     u32 PageMask,EntryHi;
193     u32 EntryLo0,EntryLo1;
194     u32 Mask, nMask;
195     u32 G;
196     u32 ASID;
197     u32 VPN2;
198     u32 PFN0;
199     u32 PFN1;
200     u32 S;
201     };
202    
203     #ifndef _PC_
204    
205     /*#define _i64(x) (s64)x
206     #define _u64(x) (u64)x
207    
208     #define _i32(x) (s32)x
209     #define _u32(x) (u32)x
210    
211     #define _i16(x) (s16)x
212     #define _u16(x) (u16)x
213    
214     #define _i8(x) (s8)x
215     #define _u8(x) (u8)x*/
216    
217     ////////////////////////////////////////////////////////////////////
218     // R5900 Instruction Macros
219    
220     #define _PC_ cpuRegs.pc // The next PC to be executed - only used in this header and R3000A.h
221    
222     #define _Funct_ ((cpuRegs.code ) & 0x3F) // The funct part of the instruction register
223     #define _Rd_ ((cpuRegs.code >> 11) & 0x1F) // The rd part of the instruction register
224     #define _Rt_ ((cpuRegs.code >> 16) & 0x1F) // The rt part of the instruction register
225     #define _Rs_ ((cpuRegs.code >> 21) & 0x1F) // The rs part of the instruction register
226     #define _Sa_ ((cpuRegs.code >> 6) & 0x1F) // The sa part of the instruction register
227     #define _Im_ ((u16)cpuRegs.code) // The immediate part of the instruction register
228     #define _Target_ (cpuRegs.code & 0x03ffffff) // The target part of the instruction register
229    
230     #define _Imm_ ((s16)cpuRegs.code) // sign-extended immediate
231     #define _ImmU_ (cpuRegs.code&0xffff) // zero-extended immediate
232     #define _ImmSB_ (cpuRegs.code&0x8000) // gets the sign-bit of the immediate value
233    
234     #define _Opcode_ (cpuRegs.code >> 26 )
235    
236     #define _JumpTarget_ ((_Target_ << 2) + (_PC_ & 0xf0000000)) // Calculates the target during a jump instruction
237     #define _BranchTarget_ (((s32)(s16)_Im_ * 4) + _PC_) // Calculates the target during a branch instruction
238     #define _TrapCode_ ((u16)cpuRegs.code >> 6) // error code for non-immediate trap instructions.
239    
240     #define _SetLink(x) (cpuRegs.GPR.r[x].UD[0] = _PC_ + 4) // Sets the return address in the link register
241    
242     #endif
243    
244     extern __aligned16 cpuRegisters cpuRegs;
245     extern __aligned16 fpuRegisters fpuRegs;
246     extern __aligned16 tlbs tlb[48];
247    
248     extern u32 g_nextBranchCycle;
249     extern bool eeEventTestIsActive;
250     extern u32 s_iLastCOP0Cycle;
251     extern u32 s_iLastPERFCycle[2];
252    
253     void intSetBranch();
254    
255     // This is a special form of the interpreter's doBranch that is run from various
256     // parts of the Recs (namely COP0's branch codes and stuff).
257     void __fastcall intDoBranch(u32 target);
258    
259     // modules loaded at hardcoded addresses by the kernel
260     const u32 EEKERNEL_START = 0;
261     const u32 EENULL_START = 0x81FC0;
262     const u32 EELOAD_START = 0x82000;
263     const u32 EELOAD_SIZE = 0x20000; // overestimate for searching
264    
265     void __fastcall eeGameStarting();
266     void __fastcall eeloadReplaceOSDSYS();
267    
268     ////////////////////////////////////////////////////////////////////
269     // R5900 Public Interface / API
270     //
271     // [TODO] : This is on the list to get converted to a proper C++ class. I'm putting it
272     // off until I get my new IOPint and IOPrec re-merged. --air
273     //
274     struct R5900cpu
275     {
276     // Memory allocation function, for allocating virtual memory spaces needed by
277     // the emulator. (ints/recs are free to allocate additional memory while running
278     // code, however any virtual mapped memory should always be allocated as soon
279     // as possible, to claim the memory before some plugin does..)
280     //
281     // Thread Affinity:
282     // Can be called from any thread. Execute status must be suspended or stopped
283     // to prevent multi-thread race conditions.
284     //
285     // Notable Exception Throws:
286     // OutOfMemory - Not enough memory, or the memory areas required were already
287     // reserved.
288     //
289     void (*Allocate)();
290    
291     // Deallocates ram allocated by Allocate and/or by runtime code execution.
292     //
293     // Thread Affinity:
294     // Can be called from any thread. Execute status must be suspended or stopped
295     // to prevent multi-thread race conditions.
296     //
297     // Exception Throws: None. This function is a destructor, and should not throw.
298     //
299     void (*Shutdown)();
300    
301     // Initializes / Resets code execution states. Typically implementation is only
302     // needed for recompilers, as interpreters have no internal execution states and
303     // rely on the CPU/VM states almost entirely.
304     //
305     // Thread Affinity:
306     // Can be called from any thread. Execute status must be suspended or stopped
307     // to prevent multi-thread race conditions.
308     //
309     // Exception Throws: Emulator-defined. Common exception types to look for:
310     // OutOfMemory, Stream Exceptions
311     //
312     void (*Reset)();
313    
314     // Steps a single instruction. Meant to be used by debuggers. Is currently unused
315     // and unimplemented. Future note: recompiler "step" should *always* fall back
316     // on interpreters.
317     //
318     // Exception Throws: [TODO] (possible execution-related throws to be added)
319     //
320     void (*Step)();
321    
322     // Executes code until a break is signaled. Execution can be paused or suspended
323     // via thread-style signals that are handled by CheckExecutionState callbacks.
324     // Execution Breakages are handled the same way, where-by a signal causes the Execute
325     // call to return at the nearest state check (typically handled internally using
326     // either C++ exceptions or setjmp/longjmp).
327     //
328     // Exception Throws: [TODO] (possible execution-related throws to be added)
329     //
330     void (*Execute)();
331    
332     // Checks for execution suspension or cancellation. In pthreads terms this provides
333     // a "cancellation point." Execution state checks are typically performed at Vsyncs
334     // by the generic VM event handlers in R5900.cpp/Counters.cpp (applies to both recs
335     // and ints).
336     //
337     // Implementation note: Because of the nuances of recompiled code execution, setjmp
338     // may be used in place of thread cancellation or C++ exceptions (non-SEH exceptions
339     // cannot unwind through the recompiled code stackframes).
340     //
341     // Thread Affinity:
342     // Must be called on the same thread as Execute only.
343     //
344     // Exception Throws:
345     // May throw threading/Pthreads cancellations if the compiler supports SEH.
346     // ThreadTimedOut - For canceling VM execution in response to MTGS deadlock. (if the
347     // core emulator does not support multithreaded GS then this will not be a throw
348     // exception).
349     //
350     void (*CheckExecutionState)();
351    
352     // Manual recompiled code cache clear; typically useful to recompilers only. Size is
353     // in MIPS words (32 bits). Dev note: this callback is nearly obsolete, and might be
354     // better off replaced with some generic API callbacks from VTLB block protection.
355     // Also: the calls from COP0's TLB remap code should be replaced with full recompiler
356     // resets, since TLB remaps affect more than just the code they contain (code that
357     // may reference the remaped blocks via memory loads/stores, for example).
358     //
359     // Thread Affinity Rule:
360     // Can be called from any thread (namely for being called from debugging threads)
361     //
362     // Exception Throws: [TODO] Emulator defined? (probably shouldn't throw, probably
363     // doesn't matter if we're stripping it out soon. ;)
364     //
365     void (*Clear)(u32 Addr, u32 Size);
366     };
367    
368     extern R5900cpu *Cpu;
369     extern R5900cpu intCpu;
370     extern R5900cpu recCpu;
371    
372     extern void cpuInit();
373     extern void cpuReset(); // can throw Exception::FileNotFound.
374     extern void cpuException(u32 code, u32 bd);
375     extern void cpuTlbMissR(u32 addr, u32 bd);
376     extern void cpuTlbMissW(u32 addr, u32 bd);
377     extern void cpuTestHwInts();
378     extern void cpuClearInt(uint n);
379    
380     extern void cpuSetNextBranch( u32 startCycle, s32 delta );
381     extern void cpuSetNextBranchDelta( s32 delta );
382     extern int cpuTestCycle( u32 startCycle, s32 delta );
383     extern void cpuSetBranch();
384    
385     extern void _cpuBranchTest_Shared(); // for internal use by the Dynarecs and Ints inside R5900:
386    
387     extern void cpuTestINTCInts();
388     extern void cpuTestDMACInts();
389     extern void cpuTestTIMRInts();
390    
391     ////////////////////////////////////////////////////////////////////
392     // Exception Codes
393    
394     #define EXC_CODE(x) ((x)<<2)
395    
396     #define EXC_CODE_Int EXC_CODE(0)
397     #define EXC_CODE_Mod EXC_CODE(1) /* TLB Modification exception */
398     #define EXC_CODE_TLBL EXC_CODE(2) /* TLB Miss exception (load or instruction fetch) */
399     #define EXC_CODE_TLBS EXC_CODE(3) /* TLB Miss exception (store) */
400     #define EXC_CODE_AdEL EXC_CODE(4)
401     #define EXC_CODE_AdES EXC_CODE(5)
402     #define EXC_CODE_IBE EXC_CODE(6)
403     #define EXC_CODE_DBE EXC_CODE(7)
404     #define EXC_CODE_Sys EXC_CODE(8)
405     #define EXC_CODE_Bp EXC_CODE(9)
406     #define EXC_CODE_Ri EXC_CODE(10)
407     #define EXC_CODE_CpU EXC_CODE(11)
408     #define EXC_CODE_Ov EXC_CODE(12)
409     #define EXC_CODE_Tr EXC_CODE(13)
410     #define EXC_CODE_FPE EXC_CODE(15)
411     #define EXC_CODE_WATCH EXC_CODE(23)
412     #define EXC_CODE__MASK 0x0000007c
413     #define EXC_CODE__SHIFT 2

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