/[pcsx2_0.9.7]/trunk/pcsx2/Memory.cpp
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revision 31 by william, Tue Sep 7 03:24:11 2010 UTC revision 62 by william, Tue Sep 7 11:08:22 2010 UTC
# Line 35  BIOS Line 35  BIOS
35  */  */
36    
37  #include "PrecompiledHeader.h"  #include "PrecompiledHeader.h"
 #include "IopCommon.h"  
   
 #pragma warning(disable:4799) // No EMMS at end of function  
   
38  #include <wx/file.h>  #include <wx/file.h>
39    
40    #include "IopCommon.h"
41  #include "VUmicro.h"  #include "VUmicro.h"
42  #include "GS.h"  #include "GS.h"
43  #include "System/PageFaultSource.h"  #include "System/PageFaultSource.h"
44    
45    #include "ps2/HwInternal.h"
46  #include "ps2/BiosTools.h"  #include "ps2/BiosTools.h"
47    
48  #ifdef ENABLECACHE  #ifdef ENABLECACHE
# Line 77  u16 ba0R16(u32 mem) Line 76  u16 ba0R16(u32 mem)
76          return 0;          return 0;
77  }  }
78    
   
 u8  *psM = NULL; //32mb Main Ram  
 u8  *psR = NULL; //4mb rom area  
 u8  *psR1 = NULL; //256kb rom1 area (actually 196kb, but can't mask this)  
 u8  *psR2 = NULL; // 0x00080000  
 u8  *psER = NULL; // 0x001C0000  
 u8  *psS = NULL; //0.015 mb, scratch pad  
   
 // Two 1 megabyte (max DMA) buffers for reading and writing to high memory (>32MB).  
 // Such accesses are not documented as causing bus errors but as the memory does  
 // not exist, reads should continue to return 0 and writes should be discarded.  
 // Probably.  
 static __aligned16 u8 highmem[0x200000];  
   
 u8  *psMHR = &highmem[0];  
 u8  *psMHW = &highmem[0x100000];  
   
79  #define CHECK_MEM(mem) //MyMemCheck(mem)  #define CHECK_MEM(mem) //MyMemCheck(mem)
80    
81  void MyMemCheck(u32 mem)  void MyMemCheck(u32 mem)
# Line 105  void MyMemCheck(u32 mem) Line 87  void MyMemCheck(u32 mem)
87  /////////////////////////////  /////////////////////////////
88  // REGULAR MEM START  // REGULAR MEM START
89  /////////////////////////////  /////////////////////////////
90  vtlbHandler null_handler;  static vtlbHandler
91            null_handler,
92    
93  vtlbHandler tlb_fallback_0;          tlb_fallback_0,
94  vtlbHandler tlb_fallback_1;          tlb_fallback_1,
95  vtlbHandler tlb_fallback_2;          tlb_fallback_2,
96  vtlbHandler tlb_fallback_3;          tlb_fallback_3,
97  vtlbHandler tlb_fallback_4;          tlb_fallback_4,
98  vtlbHandler tlb_fallback_5;          tlb_fallback_5,
99  vtlbHandler tlb_fallback_6;          tlb_fallback_6,
100  vtlbHandler tlb_fallback_7;          tlb_fallback_7,
101  vtlbHandler tlb_fallback_8;          tlb_fallback_8,
102    
103  vtlbHandler vu0_micro_mem[2];           // 0 - dynarec, 1 - interpreter          vu0_micro_mem,
104  vtlbHandler vu1_micro_mem[2];           // 0 - dynarec, 1 - interpreter          vu1_micro_mem,
105    
106  vtlbHandler hw_by_page[0x10] = { -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 };          hw_by_page[0x10] = { -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 },
107  vtlbHandler gs_page_0;  
108  vtlbHandler gs_page_1;          gs_page_0,
109            gs_page_1,
110  vtlbHandler iopHw_by_page_01;  
111  vtlbHandler iopHw_by_page_03;          iopHw_by_page_01,
112  vtlbHandler iopHw_by_page_08;          iopHw_by_page_03,
113            iopHw_by_page_08;
114    
115    
 // Used to remap the VUmicro memory according to the VU0/VU1 dynarec setting.  
 // (the VU memory operations are different for recs vs. interpreters)  
116  void memMapVUmicro()  void memMapVUmicro()
117  {  {
118          vtlb_MapHandler(vu0_micro_mem[CpuVU0->IsInterpreter],0x11000000,0x00004000);          // VU0/VU1 micro mem (instructions)
         vtlb_MapHandler(vu1_micro_mem[CpuVU1->IsInterpreter],0x11008000,0x00004000);  
   
         // VU0/VU1 memory  
119          // (Like IOP memory, these are generally only used by the EE Bios kernel during          // (Like IOP memory, these are generally only used by the EE Bios kernel during
120          //  boot-up.  Applications/games are "supposed" to use the thread-safe VIF          //  boot-up.  Applications/games are "supposed" to use the thread-safe VIF instead;
121          //  instead.)          //  or must ensure all VIF/GIF transfers are finished and all VUmicro execution stopped
122            //  prior to accessing VU memory directly).
123    
124            // The VU0 mapping actually repeats 4 times across the mapped range, but we don't bother
125            // to manually mirror it here because the indirect memory handler for it (see vuMicroRead*
126            // functions below) automatically mask and wrap the address for us.
127    
128            vtlb_MapHandler(vu0_micro_mem,0x11000000,0x00004000);
129            vtlb_MapHandler(vu1_micro_mem,0x11008000,0x00004000);
130    
131            // VU0/VU1 memory (data)
132            // VU0 is 4k, mirrored 4 times across a 16k area.
133          vtlb_MapBlock(VU0.Mem,0x11004000,0x00004000,0x1000);          vtlb_MapBlock(VU0.Mem,0x11004000,0x00004000,0x1000);
134          vtlb_MapBlock(VU1.Mem,0x1100c000,0x00004000);          vtlb_MapBlock(VU1.Mem,0x1100c000,0x00004000);
135  }  }
# Line 147  void memMapVUmicro() Line 137  void memMapVUmicro()
137  void memMapPhy()  void memMapPhy()
138  {  {
139          // Main memory          // Main memory
140          vtlb_MapBlock(psM,      0x00000000,Ps2MemSize::Base);//mirrored on first 256 mb ?          vtlb_MapBlock(eeMem->Main,      0x00000000,Ps2MemSize::Base);//mirrored on first 256 mb ?
141          // High memory, uninstalled on the configuration we emulate          // High memory, uninstalled on the configuration we emulate
142          vtlb_MapHandler(null_handler, Ps2MemSize::Base, 0x10000000 - Ps2MemSize::Base);          vtlb_MapHandler(null_handler, Ps2MemSize::Base, 0x10000000 - Ps2MemSize::Base);
143    
144          // Various ROMs (all read-only)          // Various ROMs (all read-only)
145          vtlb_MapBlock(psR,      0x1fc00000,Ps2MemSize::Rom);          vtlb_MapBlock(eeMem->ROM,       0x1fc00000,Ps2MemSize::Rom);
146          vtlb_MapBlock(psR1,     0x1e000000,Ps2MemSize::Rom1);          vtlb_MapBlock(eeMem->ROM1,      0x1e000000,Ps2MemSize::Rom1);
147          vtlb_MapBlock(psR2,     0x1e400000,Ps2MemSize::Rom2);          vtlb_MapBlock(eeMem->ROM2,      0x1e400000,Ps2MemSize::Rom2);
148          vtlb_MapBlock(psER,     0x1e040000,Ps2MemSize::ERom);          vtlb_MapBlock(eeMem->EROM,      0x1e040000,Ps2MemSize::ERom);
149    
150          // IOP memory          // IOP memory
151          // (used by the EE Bios Kernel during initial hardware initialization, Apps/Games          // (used by the EE Bios Kernel during initial hardware initialization, Apps/Games
# Line 163  void memMapPhy() Line 153  void memMapPhy()
153          vtlb_MapBlock(psxM,0x1c000000,0x00800000);          vtlb_MapBlock(psxM,0x1c000000,0x00800000);
154    
155          // Generic Handlers; These fallback to mem* stuff...          // Generic Handlers; These fallback to mem* stuff...
         vtlb_MapHandler(tlb_fallback_1,0x10000000,0x10000);  
156          vtlb_MapHandler(tlb_fallback_7,0x14000000,0x10000);          vtlb_MapHandler(tlb_fallback_7,0x14000000,0x10000);
157          vtlb_MapHandler(tlb_fallback_4,0x18000000,0x10000);          vtlb_MapHandler(tlb_fallback_4,0x18000000,0x10000);
158          vtlb_MapHandler(tlb_fallback_5,0x1a000000,0x10000);          vtlb_MapHandler(tlb_fallback_5,0x1a000000,0x10000);
# Line 175  void memMapPhy() Line 164  void memMapPhy()
164    
165          // Hardware Register Handlers : specialized/optimized per-page handling of HW register accesses          // Hardware Register Handlers : specialized/optimized per-page handling of HW register accesses
166          // (note that hw_by_page handles are assigned in memReset prior to calling this function)          // (note that hw_by_page handles are assigned in memReset prior to calling this function)
167          vtlb_MapHandler(hw_by_page[0x0], 0x10000000, 0x01000);  
168          vtlb_MapHandler(hw_by_page[0x1], 0x10001000, 0x01000);          for( uint i=0; i<16; ++i)
169          vtlb_MapHandler(hw_by_page[0x2], 0x10002000, 0x01000);                  vtlb_MapHandler(hw_by_page[i], 0x10000000 + (0x01000 * i), 0x01000);
         vtlb_MapHandler(hw_by_page[0x3], 0x10003000, 0x01000);  
         vtlb_MapHandler(hw_by_page[0x4], 0x10004000, 0x01000);  
         vtlb_MapHandler(hw_by_page[0x5], 0x10005000, 0x01000);  
         vtlb_MapHandler(hw_by_page[0x6], 0x10006000, 0x01000);  
         vtlb_MapHandler(hw_by_page[0x7], 0x10007000, 0x01000);  
         vtlb_MapHandler(hw_by_page[0xb], 0x1000b000, 0x01000);  
         vtlb_MapHandler(hw_by_page[0xe], 0x1000e000, 0x01000);  
         vtlb_MapHandler(hw_by_page[0xf], 0x1000f000, 0x01000);  
170    
171          vtlb_MapHandler(gs_page_0, 0x12000000, 0x01000);          vtlb_MapHandler(gs_page_0, 0x12000000, 0x01000);
172          vtlb_MapHandler(gs_page_1, 0x12001000, 0x01000);          vtlb_MapHandler(gs_page_1, 0x12001000, 0x01000);
# Line 237  static void __fastcall nullRead64(u32 me Line 218  static void __fastcall nullRead64(u32 me
218  }  }
219  static void __fastcall nullRead128(u32 mem, mem128_t *out) {  static void __fastcall nullRead128(u32 mem, mem128_t *out) {
220          MEM_LOG("Read uninstalled memory at address %08x", mem);          MEM_LOG("Read uninstalled memory at address %08x", mem);
221          *out = 0;          ZeroQWC(out);
222  }  }
223  static void __fastcall nullWrite8(u32 mem, mem8_t value)  static void __fastcall nullWrite8(u32 mem, mem8_t value)
224  {  {
# Line 261  static void __fastcall nullWrite128(u32 Line 242  static void __fastcall nullWrite128(u32
242  }  }
243    
244  template<int p>  template<int p>
245  mem8_t __fastcall _ext_memRead8 (u32 mem)  static mem8_t __fastcall _ext_memRead8 (u32 mem)
246  {  {
247          switch (p)          switch (p)
248          {          {
                 case 1: // hwm  
                         return hwRead8(mem);  
249                  case 3: // psh4                  case 3: // psh4
250                          return psxHw4Read8(mem);                          return psxHw4Read8(mem);
251                  case 6: // gsm                  case 6: // gsm
# Line 285  mem8_t __fastcall _ext_memRead8 (u32 mem Line 264  mem8_t __fastcall _ext_memRead8 (u32 mem
264  }  }
265    
266  template<int p>  template<int p>
267  mem16_t __fastcall _ext_memRead16(u32 mem)  static mem16_t __fastcall _ext_memRead16(u32 mem)
268  {  {
269          switch (p)          switch (p)
270          {          {
                 case 1: // hwm  
                         return hwRead16(mem);  
271                  case 4: // b80                  case 4: // b80
272                          MEM_LOG("b800000 Memory read16 address %x", mem);                          MEM_LOG("b800000 Memory read16 address %x", mem);
273                          return 0;                          return 0;
# Line 315  mem16_t __fastcall _ext_memRead16(u32 me Line 292  mem16_t __fastcall _ext_memRead16(u32 me
292  }  }
293    
294  template<int p>  template<int p>
295  mem32_t __fastcall _ext_memRead32(u32 mem)  static mem32_t __fastcall _ext_memRead32(u32 mem)
296  {  {
297          switch (p)          switch (p)
298          {          {
# Line 335  mem32_t __fastcall _ext_memRead32(u32 me Line 312  mem32_t __fastcall _ext_memRead32(u32 me
312  }  }
313    
314  template<int p>  template<int p>
315  void __fastcall _ext_memRead64(u32 mem, mem64_t *out)  static void __fastcall _ext_memRead64(u32 mem, mem64_t *out)
316  {  {
317          switch (p)          switch (p)
318          {          {
# Line 348  void __fastcall _ext_memRead64(u32 mem, Line 325  void __fastcall _ext_memRead64(u32 mem,
325  }  }
326    
327  template<int p>  template<int p>
328  void __fastcall _ext_memRead128(u32 mem, mem128_t *out)  static void __fastcall _ext_memRead128(u32 mem, mem128_t *out)
329  {  {
330          switch (p)          switch (p)
331          {          {
332                  //case 1: // hwm                  //case 1: // hwm
333                  //      hwRead128(mem & ~0xa0000000, out); return;                  //      hwRead128(mem & ~0xa0000000, out); return;
334                  case 6: // gsm                  case 6: // gsm
335                          out[0] = gsRead64(mem  );                          CopyQWC(out,PS2GS_BASE(mem));
336                          out[1] = gsRead64(mem+8); return;                  return;
337          }          }
338    
339          MEM_LOG("Unknown Memory read128 from address %8.8x", mem);          MEM_LOG("Unknown Memory read128 from address %8.8x", mem);
# Line 364  void __fastcall _ext_memRead128(u32 mem, Line 341  void __fastcall _ext_memRead128(u32 mem,
341  }  }
342    
343  template<int p>  template<int p>
344  void __fastcall _ext_memWrite8 (u32 mem, mem8_t  value)  static void __fastcall _ext_memWrite8 (u32 mem, mem8_t  value)
345  {  {
346          switch (p) {          switch (p) {
                 case 1: // hwm  
                         hwWrite8(mem, value);  
                         return;  
347                  case 3: // psh4                  case 3: // psh4
348                          psxHw4Write8(mem, value); return;                          psxHw4Write8(mem, value); return;
349                  case 6: // gsm                  case 6: // gsm
# Line 383  void __fastcall _ext_memWrite8 (u32 mem, Line 357  void __fastcall _ext_memWrite8 (u32 mem,
357          MEM_LOG("Unknown Memory write8   to  address %x with data %2.2x", mem, value);          MEM_LOG("Unknown Memory write8   to  address %x with data %2.2x", mem, value);
358          cpuTlbMissW(mem, cpuRegs.branch);          cpuTlbMissW(mem, cpuRegs.branch);
359  }  }
360    
361  template<int p>  template<int p>
362  void __fastcall _ext_memWrite16(u32 mem, mem16_t value)  static void __fastcall _ext_memWrite16(u32 mem, mem16_t value)
363  {  {
364          switch (p) {          switch (p) {
                 case 1: // hwm  
                         hwWrite16(mem, value);  
                         return;  
365                  case 5: // ba0                  case 5: // ba0
366                          MEM_LOG("ba00000 Memory write16 to  address %x with data %x", mem, value);                          MEM_LOG("ba00000 Memory write16 to  address %x with data %x", mem, value);
367                          return;                          return;
# Line 407  void __fastcall _ext_memWrite16(u32 mem, Line 379  void __fastcall _ext_memWrite16(u32 mem,
379  }  }
380    
381  template<int p>  template<int p>
382  void __fastcall _ext_memWrite32(u32 mem, mem32_t value)  static void __fastcall _ext_memWrite32(u32 mem, mem32_t value)
383  {  {
384          switch (p) {          switch (p) {
385                  case 6: // gsm                  case 6: // gsm
# Line 422  void __fastcall _ext_memWrite32(u32 mem, Line 394  void __fastcall _ext_memWrite32(u32 mem,
394  }  }
395    
396  template<int p>  template<int p>
397  void __fastcall _ext_memWrite64(u32 mem, const mem64_t* value)  static void __fastcall _ext_memWrite64(u32 mem, const mem64_t* value)
398  {  {
399    
400          /*switch (p) {          /*switch (p) {
# Line 438  void __fastcall _ext_memWrite64(u32 mem, Line 410  void __fastcall _ext_memWrite64(u32 mem,
410  }  }
411    
412  template<int p>  template<int p>
413  void __fastcall _ext_memWrite128(u32 mem, const mem128_t *value)  static void __fastcall _ext_memWrite128(u32 mem, const mem128_t *value)
414  {  {
415          /*switch (p) {          /*switch (p) {
416                  //case 1: // hwm                  //case 1: // hwm
# Line 457  void __fastcall _ext_memWrite128(u32 mem Line 429  void __fastcall _ext_memWrite128(u32 mem
429  #define vtlb_RegisterHandlerTempl1(nam,t) vtlb_RegisterHandler(nam##Read8<t>,nam##Read16<t>,nam##Read32<t>,nam##Read64<t>,nam##Read128<t>, \  #define vtlb_RegisterHandlerTempl1(nam,t) vtlb_RegisterHandler(nam##Read8<t>,nam##Read16<t>,nam##Read32<t>,nam##Read64<t>,nam##Read128<t>, \
430                                                                                                                             nam##Write8<t>,nam##Write16<t>,nam##Write32<t>,nam##Write64<t>,nam##Write128<t>)                                                                                                                             nam##Write8<t>,nam##Write16<t>,nam##Write32<t>,nam##Write64<t>,nam##Write128<t>)
431    
 #define vtlb_RegisterHandlerTempl2(nam,t,rec) vtlb_RegisterHandler(nam##Read8<t>,nam##Read16<t>,nam##Read32<t>,nam##Read64<t>,nam##Read128<t>, \  
                                                                                                                                    nam##Write8<t,rec>,nam##Write16<t,rec>,nam##Write32<t,rec>,nam##Write64<t,rec>,nam##Write128<t,rec>)  
   
432  typedef void __fastcall ClearFunc_t( u32 addr, u32 qwc );  typedef void __fastcall ClearFunc_t( u32 addr, u32 qwc );
433    
434  template<int vunum, bool dynarec>  template<int vunum>
435  static __forceinline void ClearVuFunc( u32 addr, u32 size )  static __fi void ClearVuFunc( u32 addr, u32 size )
436  {  {
437          if( dynarec )          if( vunum==0 )
438          {                  CpuVU0->Clear(addr,size);
                 if( vunum==0 )  
                         CpuVU0->Clear(addr,size);  
                 else  
                         CpuVU1->Clear(addr,size);  
         }  
439          else          else
440          {                  CpuVU1->Clear(addr,size);
                 if( vunum==0 )  
                         CpuVU0->Clear(addr,size);  
                 else  
                         CpuVU1->Clear(addr,size);  
         }  
441  }  }
442    
443  template<int vunum>  template<int vunum>
444  mem8_t __fastcall vuMicroRead8(u32 addr)  static mem8_t __fastcall vuMicroRead8(u32 addr)
445  {  {
446          addr&=(vunum==0)?0xfff:0x3fff;          addr&=(vunum==0)?0xfff:0x3fff;
447          VURegs* vu=(vunum==0)?&VU0:&VU1;          VURegs* vu=(vunum==0)?&VU0:&VU1;
# Line 491  mem8_t __fastcall vuMicroRead8(u32 addr) Line 450  mem8_t __fastcall vuMicroRead8(u32 addr)
450  }  }
451    
452  template<int vunum>  template<int vunum>
453  mem16_t __fastcall vuMicroRead16(u32 addr)  static mem16_t __fastcall vuMicroRead16(u32 addr)
454  {  {
455          addr&=(vunum==0)?0xfff:0x3fff;          addr&=(vunum==0)?0xfff:0x3fff;
456          VURegs* vu=(vunum==0)?&VU0:&VU1;          VURegs* vu=(vunum==0)?&VU0:&VU1;
# Line 500  mem16_t __fastcall vuMicroRead16(u32 add Line 459  mem16_t __fastcall vuMicroRead16(u32 add
459  }  }
460    
461  template<int vunum>  template<int vunum>
462  mem32_t __fastcall vuMicroRead32(u32 addr)  static mem32_t __fastcall vuMicroRead32(u32 addr)
463  {  {
464          addr&=(vunum==0)?0xfff:0x3fff;          addr&=(vunum==0)?0xfff:0x3fff;
465          VURegs* vu=(vunum==0)?&VU0:&VU1;          VURegs* vu=(vunum==0)?&VU0:&VU1;
# Line 509  mem32_t __fastcall vuMicroRead32(u32 add Line 468  mem32_t __fastcall vuMicroRead32(u32 add
468  }  }
469    
470  template<int vunum>  template<int vunum>
471  void __fastcall vuMicroRead64(u32 addr,mem64_t* data)  static void __fastcall vuMicroRead64(u32 addr,mem64_t* data)
472  {  {
473          addr&=(vunum==0)?0xfff:0x3fff;          addr&=(vunum==0)?0xfff:0x3fff;
474          VURegs* vu=(vunum==0)?&VU0:&VU1;          VURegs* vu=(vunum==0)?&VU0:&VU1;
# Line 518  void __fastcall vuMicroRead64(u32 addr,m Line 477  void __fastcall vuMicroRead64(u32 addr,m
477  }  }
478    
479  template<int vunum>  template<int vunum>
480  void __fastcall vuMicroRead128(u32 addr,mem128_t* data)  static void __fastcall vuMicroRead128(u32 addr,mem128_t* data)
481  {  {
482          addr&=(vunum==0)?0xfff:0x3fff;          addr&=(vunum==0)?0xfff:0x3fff;
483          VURegs* vu=(vunum==0)?&VU0:&VU1;          VURegs* vu=(vunum==0)?&VU0:&VU1;
484    
485          data[0]=*(u64*)&vu->Micro[addr];          CopyQWC(data,&vu->Micro[addr]);
         data[1]=*(u64*)&vu->Micro[addr+8];  
486  }  }
487    
488  // Profiled VU writes: Happen very infrequently, with exception of BIOS initialization (at most twice per  // Profiled VU writes: Happen very infrequently, with exception of BIOS initialization (at most twice per
489  //   frame in-game, and usually none at all after BIOS), so cpu clears aren't much of a big deal.  //   frame in-game, and usually none at all after BIOS), so cpu clears aren't much of a big deal.
490    
491  template<int vunum, bool dynrec>  template<int vunum>
492  void __fastcall vuMicroWrite8(u32 addr,mem8_t data)  static void __fastcall vuMicroWrite8(u32 addr,mem8_t data)
493  {  {
494          addr &= (vunum==0) ? 0xfff : 0x3fff;          addr &= (vunum==0) ? 0xfff : 0x3fff;
495          VURegs& vu = (vunum==0) ? VU0 : VU1;          VURegs& vu = (vunum==0) ? VU0 : VU1;
496    
497          if (vu.Micro[addr]!=data)          if (vu.Micro[addr]!=data)
498          {          {
499                  ClearVuFunc<vunum, dynrec>(addr&(~7), 8); // Clear before writing new data (clearing 8 bytes because an instruction is 8 bytes) (cottonvibes)                  ClearVuFunc<vunum>(addr&(~7), 8); // Clear before writing new data (clearing 8 bytes because an instruction is 8 bytes) (cottonvibes)
500                  vu.Micro[addr]=data;                  vu.Micro[addr]=data;
501          }          }
502  }  }
503    
504  template<int vunum, bool dynrec>  template<int vunum>
505  void __fastcall vuMicroWrite16(u32 addr,mem16_t data)  static void __fastcall vuMicroWrite16(u32 addr,mem16_t data)
506  {  {
507          addr &= (vunum==0) ? 0xfff : 0x3fff;          addr &= (vunum==0) ? 0xfff : 0x3fff;
508          VURegs& vu = (vunum==0) ? VU0 : VU1;          VURegs& vu = (vunum==0) ? VU0 : VU1;
509    
510          if (*(u16*)&vu.Micro[addr]!=data)          if (*(u16*)&vu.Micro[addr]!=data)
511          {          {
512                  ClearVuFunc<vunum, dynrec>(addr&(~7), 8);                  ClearVuFunc<vunum>(addr&(~7), 8);
513                  *(u16*)&vu.Micro[addr]=data;                  *(u16*)&vu.Micro[addr]=data;
514          }          }
515  }  }
516    
517  template<int vunum, bool dynrec>  template<int vunum>
518  void __fastcall vuMicroWrite32(u32 addr,mem32_t data)  static void __fastcall vuMicroWrite32(u32 addr,mem32_t data)
519  {  {
520          addr &= (vunum==0) ? 0xfff : 0x3fff;          addr &= (vunum==0) ? 0xfff : 0x3fff;
521          VURegs& vu = (vunum==0) ? VU0 : VU1;          VURegs& vu = (vunum==0) ? VU0 : VU1;
522    
523          if (*(u32*)&vu.Micro[addr]!=data)          if (*(u32*)&vu.Micro[addr]!=data)
524          {          {
525                  ClearVuFunc<vunum, dynrec>(addr&(~7), 8);                  ClearVuFunc<vunum>(addr&(~7), 8);
526                  *(u32*)&vu.Micro[addr]=data;                  *(u32*)&vu.Micro[addr]=data;
527          }          }
528  }  }
529    
530  template<int vunum, bool dynrec>  template<int vunum>
531  void __fastcall vuMicroWrite64(u32 addr,const mem64_t* data)  static void __fastcall vuMicroWrite64(u32 addr,const mem64_t* data)
532  {  {
533          addr &= (vunum==0) ? 0xfff : 0x3fff;          addr &= (vunum==0) ? 0xfff : 0x3fff;
534          VURegs& vu = (vunum==0) ? VU0 : VU1;          VURegs& vu = (vunum==0) ? VU0 : VU1;
535    
536          if (*(u64*)&vu.Micro[addr]!=data[0])          if (*(u64*)&vu.Micro[addr]!=data[0])
537          {          {
538                  ClearVuFunc<vunum, dynrec>(addr&(~7), 8);                  ClearVuFunc<vunum>(addr&(~7), 8);
539                  *(u64*)&vu.Micro[addr]=data[0];                  *(u64*)&vu.Micro[addr]=data[0];
540          }          }
541  }  }
542    
543  template<int vunum, bool dynrec>  template<int vunum>
544  void __fastcall vuMicroWrite128(u32 addr,const mem128_t* data)  static void __fastcall vuMicroWrite128(u32 addr,const mem128_t* data)
545  {  {
546          addr &= (vunum==0) ? 0xfff : 0x3fff;          addr &= (vunum==0) ? 0xfff : 0x3fff;
547          VURegs& vu = (vunum==0) ? VU0 : VU1;          VURegs& vu = (vunum==0) ? VU0 : VU1;
548    
549          if (*(u64*)&vu.Micro[addr]!=data[0] || *(u64*)&vu.Micro[addr+8]!=data[1])          if ((u128&)vu.Micro[addr] != *data)
550          {          {
551                  ClearVuFunc<vunum, dynrec>(addr&(~7), 16);                  ClearVuFunc<vunum>(addr&(~7), 16);
552                  *(u64*)&vu.Micro[addr]=data[0];                  CopyQWC(&vu.Micro[addr],data);
                 *(u64*)&vu.Micro[addr+8]=data[1];  
553          }          }
554  }  }
555    
# Line 625  protected: Line 582  protected:
582          void OnPageFaultEvent( const PageFaultInfo& info, bool& handled );          void OnPageFaultEvent( const PageFaultInfo& info, bool& handled );
583  };  };
584    
585  mmap_PageFaultHandler mmap_faultHandler;  static mmap_PageFaultHandler mmap_faultHandler;
586    
587  static const uint m_allMemSize =  EEVM_MemoryAllocMess* eeMem = NULL;
                 Ps2MemSize::Rom + Ps2MemSize::Rom1 + Ps2MemSize::Rom2 + Ps2MemSize::ERom +  
                 Ps2MemSize::Base + Ps2MemSize::Hardware + Ps2MemSize::Scratch;  
588    
589  static u8* m_psAllMem = NULL;  __pagealigned u8 eeHw[Ps2MemSize::Hardware];
590    
591  void memAlloc()  void memAlloc()
592  {  {
593          if( m_psAllMem == NULL )          if( eeMem == NULL )
594                  m_psAllMem = vtlb_malloc( m_allMemSize, 4096 );                  eeMem = (EEVM_MemoryAllocMess*)vtlb_malloc( sizeof(*eeMem), 4096 );
595    
596          if( m_psAllMem == NULL)          if( eeMem == NULL)
597                  throw Exception::OutOfMemory( "memAlloc > failed to allocate PS2's base ram/rom/scratchpad." );                  throw Exception::OutOfMemory( L"memAlloc > failed to allocate PS2's base ram/rom/scratchpad." );
   
         u8* curpos = m_psAllMem;  
         psM = curpos; curpos += Ps2MemSize::Base;  
         psR = curpos; curpos += Ps2MemSize::Rom;  
         psR1 = curpos; curpos += Ps2MemSize::Rom1;  
         psR2 = curpos; curpos += Ps2MemSize::Rom2;  
         psER = curpos; curpos += Ps2MemSize::ERom;  
         psH = curpos; curpos += Ps2MemSize::Hardware;  
         psS = curpos; //curpos += Ps2MemSize::Scratch;  
598    
599          Source_PageFault.Add( mmap_faultHandler );          Source_PageFault.Add( mmap_faultHandler );
600  }  }
# Line 657  void memShutdown() Line 603  void memShutdown()
603  {  {
604          Source_PageFault.Remove( mmap_faultHandler );          Source_PageFault.Remove( mmap_faultHandler );
605    
606          vtlb_free( m_psAllMem, m_allMemSize );          vtlb_free( eeMem, sizeof(*eeMem) );
607          m_psAllMem = NULL;          eeMem = NULL;
         psM = psR = psR1 = psR2 = psER = psS = psH = NULL;  
608          vtlb_Term();          vtlb_Term();
609  }  }
610    
# Line 667  void memBindConditionalHandlers() Line 612  void memBindConditionalHandlers()
612  {  {
613          if( hw_by_page[0xf] == -1 ) return;          if( hw_by_page[0xf] == -1 ) return;
614    
615          vtlbMemR32FP* page0F32( EmuConfig.Speedhacks.IntcStat ? hwRead32_page_0F_INTC_HACK : hwRead32_page_0F );          if (EmuConfig.Speedhacks.IntcStat)
616          vtlbMemR64FP* page0F64( EmuConfig.Speedhacks.IntcStat ? hwRead64_generic_INTC_HACK : hwRead64_generic );          {
617                    vtlbMemR16FP* page0F16(hwRead16_page_0F_INTC_HACK);
618          vtlb_ReassignHandler( hw_by_page[0xf],                  vtlbMemR32FP* page0F32(hwRead32_page_0F_INTC_HACK);
619                  _ext_memRead8<1>, _ext_memRead16<1>, page0F32, page0F64, hwRead128_generic,                  //vtlbMemR64FP* page0F64(hwRead64_generic_INTC_HACK);
620                  _ext_memWrite8<1>, _ext_memWrite16<1>, hwWrite32_page_0F, hwWrite64_generic, hwWrite128_generic  
621          );                  vtlb_ReassignHandler( hw_by_page[0xf],
622                            hwRead8<0x0f>,  page0F16,                       page0F32,                       hwRead64<0x0f>,         hwRead128<0x0f>,
623                            hwWrite8<0x0f>, hwWrite16<0x0f>,        hwWrite32<0x0f>,        hwWrite64<0x0f>,        hwWrite128<0x0f>
624                    );
625            }
626            else
627            {
628                    vtlbMemR16FP* page0F16(hwRead16<0x0f>);
629                    vtlbMemR32FP* page0F32(hwRead32<0x0f>);
630                    //vtlbMemR64FP* page0F64(hwRead64<0x0f>);
631    
632                    vtlb_ReassignHandler( hw_by_page[0xf],
633                            hwRead8<0x0f>,  page0F16,                       page0F32,                       hwRead64<0x0f>,         hwRead128<0x0f>,
634                            hwWrite8<0x0f>, hwWrite16<0x0f>,        hwWrite32<0x0f>,        hwWrite64<0x0f>,        hwWrite128<0x0f>
635                    );
636            }
637  }  }
638    
639  // Resets memory mappings, unmaps TLBs, reloads bios roms, etc.  // Resets memory mappings, unmaps TLBs, reloads bios roms, etc.
# Line 687  void memReset() Line 647  void memReset()
647          // rest of the emu is not really set up to support a "soft" reset of that sort          // rest of the emu is not really set up to support a "soft" reset of that sort
648          // we opt for the hard/safe version.          // we opt for the hard/safe version.
649    
650          memzero_ptr<m_allMemSize>( m_psAllMem );          memzero( *eeMem );
651  #ifdef ENABLECACHE  #ifdef ENABLECACHE
652          memset(pCache,0,sizeof(_cacheS)*64);          memset(pCache,0,sizeof(_cacheS)*64);
653  #endif  #endif
# Line 701  void memReset() Line 661  void memReset()
661          tlb_fallback_3 = vtlb_RegisterHandlerTempl1(_ext_mem,3);          tlb_fallback_3 = vtlb_RegisterHandlerTempl1(_ext_mem,3);
662          tlb_fallback_4 = vtlb_RegisterHandlerTempl1(_ext_mem,4);          tlb_fallback_4 = vtlb_RegisterHandlerTempl1(_ext_mem,4);
663          tlb_fallback_5 = vtlb_RegisterHandlerTempl1(_ext_mem,5);          tlb_fallback_5 = vtlb_RegisterHandlerTempl1(_ext_mem,5);
         //tlb_fallback_6 = vtlb_RegisterHandlerTempl1(_ext_mem,6);  
664          tlb_fallback_7 = vtlb_RegisterHandlerTempl1(_ext_mem,7);          tlb_fallback_7 = vtlb_RegisterHandlerTempl1(_ext_mem,7);
665          tlb_fallback_8 = vtlb_RegisterHandlerTempl1(_ext_mem,8);          tlb_fallback_8 = vtlb_RegisterHandlerTempl1(_ext_mem,8);
666    
667          // Dynarec versions of VUs          // Dynarec versions of VUs
668          vu0_micro_mem[0] = vtlb_RegisterHandlerTempl2(vuMicro,0,true);          vu0_micro_mem = vtlb_RegisterHandlerTempl1(vuMicro,0);
669          vu1_micro_mem[0] = vtlb_RegisterHandlerTempl2(vuMicro,1,true);          vu1_micro_mem = vtlb_RegisterHandlerTempl1(vuMicro,1);
   
         // Interpreter versions of VUs  
         vu0_micro_mem[1] = vtlb_RegisterHandlerTempl2(vuMicro,0,false);  
         vu1_micro_mem[1] = vtlb_RegisterHandlerTempl2(vuMicro,1,false);  
670    
671          //////////////////////////////////////////////////////////////////////////////////////////          //////////////////////////////////////////////////////////////////////////////////////////
672          // IOP's "secret" Hardware Register mapping, accessible from the EE (and meant for use          // IOP's "secret" Hardware Register mapping, accessible from the EE (and meant for use
# Line 742  void memReset() Line 697  void memReset()
697          );          );
698    
699    
         //////////////////////////////////////////////////////////////////////////////////////////  
700          // psHw Optimized Mappings          // psHw Optimized Mappings
701          // The HW Registers have been split into pages to improve optimization.          // The HW Registers have been split into pages to improve optimization.
702          // Anything not explicitly mapped into one of the hw_by_page handlers will be handled          
703          // by the default/generic tlb_fallback_1 handler.  #define hwHandlerTmpl(page) \
704            hwRead8<page>,  hwRead16<page>, hwRead32<page>, hwRead64<page>, hwRead128<page>, \
705          tlb_fallback_1 = vtlb_RegisterHandler(          hwWrite8<page>, hwWrite16<page>,hwWrite32<page>,hwWrite64<page>,hwWrite128<page>
706                  _ext_memRead8<1>, _ext_memRead16<1>, hwRead32_generic, hwRead64_generic, hwRead128_generic,  
707                  _ext_memWrite8<1>, _ext_memWrite16<1>, hwWrite32_generic, hwWrite64_generic, hwWrite128_generic          hw_by_page[0x0] = vtlb_RegisterHandler( hwHandlerTmpl(0x00) );
708          );          hw_by_page[0x1] = vtlb_RegisterHandler( hwHandlerTmpl(0x01) );
709            hw_by_page[0x2] = vtlb_RegisterHandler( hwHandlerTmpl(0x02) );
710          hw_by_page[0x0] = vtlb_RegisterHandler(          hw_by_page[0x3] = vtlb_RegisterHandler( hwHandlerTmpl(0x03) );
711                  _ext_memRead8<1>, _ext_memRead16<1>, hwRead32_page_00, hwRead64_page_00, hwRead128_page_00,          hw_by_page[0x4] = vtlb_RegisterHandler( hwHandlerTmpl(0x04) );
712                  _ext_memWrite8<1>, _ext_memWrite16<1>, hwWrite32_page_00, hwWrite64_page_00, hwWrite128_generic          hw_by_page[0x5] = vtlb_RegisterHandler( hwHandlerTmpl(0x05) );
713          );          hw_by_page[0x6] = vtlb_RegisterHandler( hwHandlerTmpl(0x06) );
714            hw_by_page[0x7] = vtlb_RegisterHandler( hwHandlerTmpl(0x07) );
715          hw_by_page[0x1] = vtlb_RegisterHandler(          hw_by_page[0x8] = vtlb_RegisterHandler( hwHandlerTmpl(0x08) );
716                  _ext_memRead8<1>, _ext_memRead16<1>, hwRead32_page_01, hwRead64_page_01, hwRead128_page_01,          hw_by_page[0x9] = vtlb_RegisterHandler( hwHandlerTmpl(0x09) );
717                  _ext_memWrite8<1>, _ext_memWrite16<1>, hwWrite32_page_01, hwWrite64_page_01, hwWrite128_generic          hw_by_page[0xa] = vtlb_RegisterHandler( hwHandlerTmpl(0x0a) );
718          );          hw_by_page[0xb] = vtlb_RegisterHandler( hwHandlerTmpl(0x0b) );
719            hw_by_page[0xc] = vtlb_RegisterHandler( hwHandlerTmpl(0x0c) );
720          hw_by_page[0x2] = vtlb_RegisterHandler(          hw_by_page[0xd] = vtlb_RegisterHandler( hwHandlerTmpl(0x0d) );
721                  _ext_memRead8<1>, _ext_memRead16<1>, hwRead32_page_02, hwRead64_page_02, hwRead128_page_02,          hw_by_page[0xe] = vtlb_RegisterHandler( hwHandlerTmpl(0x0e) );
722                  _ext_memWrite8<1>, _ext_memWrite16<1>, hwWrite32_page_02, hwWrite64_page_02, hwWrite128_generic          hw_by_page[0xf] = vtlb_NewHandler();            // redefined later based on speedhacking prefs
         );  
   
         hw_by_page[0x3] = vtlb_RegisterHandler(  
                 _ext_memRead8<1>, _ext_memRead16<1>, hwRead32_generic, hwRead64_generic, hwRead128_generic,  
                 _ext_memWrite8<1>, _ext_memWrite16<1>, hwWrite32_page_03, hwWrite64_page_03, hwWrite128_generic  
         );  
   
         hw_by_page[0x4] = vtlb_RegisterHandler(  
                 _ext_memRead8<1>, _ext_memRead16<1>, hwRead32_generic, hwRead64_generic, ReadFIFO_page_4,  
                 _ext_memWrite8<1>, _ext_memWrite16<1>, hwWrite32_generic, hwWrite64_generic, WriteFIFO_page_4  
         );  
   
         hw_by_page[0x5] = vtlb_RegisterHandler(  
                 _ext_memRead8<1>, _ext_memRead16<1>, hwRead32_generic, hwRead64_generic, ReadFIFO_page_5,  
                 _ext_memWrite8<1>, _ext_memWrite16<1>, hwWrite32_generic, hwWrite64_generic, WriteFIFO_page_5  
         );  
   
         hw_by_page[0x6] = vtlb_RegisterHandler(  
                 _ext_memRead8<1>, _ext_memRead16<1>, hwRead32_generic, hwRead64_generic, ReadFIFO_page_6,  
                 _ext_memWrite8<1>, _ext_memWrite16<1>, hwWrite32_generic, hwWrite64_generic, WriteFIFO_page_6  
         );  
   
         hw_by_page[0x7] = vtlb_RegisterHandler(  
                 _ext_memRead8<1>, _ext_memRead16<1>, hwRead32_generic, hwRead64_generic, ReadFIFO_page_7,  
                 _ext_memWrite8<1>, _ext_memWrite16<1>, hwWrite32_generic, hwWrite64_generic, WriteFIFO_page_7  
         );  
   
         hw_by_page[0xb] = vtlb_RegisterHandler(  
                 _ext_memRead8<1>, _ext_memRead16<1>, hwRead32_generic, hwRead64_generic, hwRead128_generic,  
                 _ext_memWrite8<1>, _ext_memWrite16<1>, hwWrite32_page_0B, hwWrite64_generic, hwWrite128_generic  
         );  
   
         hw_by_page[0xe] = vtlb_RegisterHandler(  
                 _ext_memRead8<1>, _ext_memRead16<1>, hwRead32_generic, hwRead64_generic, hwRead128_generic,  
                 _ext_memWrite8<1>, _ext_memWrite16<1>, hwWrite32_page_0E, hwWrite64_page_0E, hwWrite128_generic  
         );  
   
         hw_by_page[0xf] = vtlb_NewHandler();  
723          memBindConditionalHandlers();          memBindConditionalHandlers();
724    
725          //////////////////////////////////////////////////////////////////////          //////////////////////////////////////////////////////////////////////
# Line 900  int mmap_GetRamPageInfo( u32 paddr ) Line 816  int mmap_GetRamPageInfo( u32 paddr )
816          paddr &= ~0xfff;          paddr &= ~0xfff;
817    
818          uptr ptr = (uptr)PSM( paddr );          uptr ptr = (uptr)PSM( paddr );
819          uptr rampage = ptr - (uptr)psM;          uptr rampage = ptr - (uptr)eeMem->Main;
820    
821          if (rampage >= Ps2MemSize::Base)          if (rampage >= Ps2MemSize::Base)
822                  return -1; //not in ram, no tracking done ...                  return -1; //not in ram, no tracking done ...
# Line 915  void mmap_MarkCountedRamPage( u32 paddr Line 831  void mmap_MarkCountedRamPage( u32 paddr
831          paddr &= ~0xfff;          paddr &= ~0xfff;
832    
833          uptr ptr = (uptr)PSM( paddr );          uptr ptr = (uptr)PSM( paddr );
834          int rampage = (ptr - (uptr)psM) >> 12;          int rampage = (ptr - (uptr)eeMem->Main) >> 12;
835    
836          // Important: reassign paddr here, since TLB changes could alter the paddr->psM mapping          // Important: reassign paddr here, since TLB changes could alter the paddr->psM mapping
837          // (and clear blocks accordingly), but don't necessarily clear the protection status.          // (and clear blocks accordingly), but don't necessarily clear the protection status.
# Line 924  void mmap_MarkCountedRamPage( u32 paddr Line 840  void mmap_MarkCountedRamPage( u32 paddr
840          if( m_PageProtectInfo[rampage].Mode == ProtMode_Write )          if( m_PageProtectInfo[rampage].Mode == ProtMode_Write )
841                  return;         // skip town if we're already protected.                  return;         // skip town if we're already protected.
842    
843          DbgCon.WriteLn( Color_Gray, (m_PageProtectInfo[rampage].Mode == ProtMode_Manual) ?          eeRecPerfLog.Write( (m_PageProtectInfo[rampage].Mode == ProtMode_Manual) ?
844                  "dyna_page_reset @ 0x%05x" : "Write-protected page @ 0x%05x",                  "Re-protecting page @ 0x%05x" : "Protected page @ 0x%05x",
845                  paddr>>12                  paddr>>12
846          );          );
847    
848          m_PageProtectInfo[rampage].Mode = ProtMode_Write;          m_PageProtectInfo[rampage].Mode = ProtMode_Write;
849          HostSys::MemProtect( &psM[rampage<<12], __pagesize, Protect_ReadOnly );          HostSys::MemProtect( &eeMem->Main[rampage<<12], __pagesize, Protect_ReadOnly );
850  }  }
851    
852  // offset - offset of address relative to psM.  // offset - offset of address relative to psM.
853  static __forceinline void mmap_ClearCpuBlock( uint offset )  // All recompiled blocks belonging to the page are cleared, and any new blocks recompiled
854    // from code residing in this page will use manual protection.
855    static __fi void mmap_ClearCpuBlock( uint offset )
856  {  {
857          int rampage = offset >> 12;          int rampage = offset >> 12;
858    
# Line 943  static __forceinline void mmap_ClearCpuB Line 861  static __forceinline void mmap_ClearCpuB
861          pxAssertMsg( m_PageProtectInfo[rampage].Mode != ProtMode_Manual,          pxAssertMsg( m_PageProtectInfo[rampage].Mode != ProtMode_Manual,
862                  "Attempted to clear a block that is already under manual protection." );                  "Attempted to clear a block that is already under manual protection." );
863    
864          HostSys::MemProtect( &psM[rampage<<12], __pagesize, Protect_ReadWrite );          HostSys::MemProtect( &eeMem->Main[rampage<<12], __pagesize, Protect_ReadWrite );
865          m_PageProtectInfo[rampage].Mode = ProtMode_Manual;          m_PageProtectInfo[rampage].Mode = ProtMode_Manual;
866          Cpu->Clear( m_PageProtectInfo[rampage].ReverseRamMap, 0x400 );          Cpu->Clear( m_PageProtectInfo[rampage].ReverseRamMap, 0x400 );
867  }  }
# Line 951  static __forceinline void mmap_ClearCpuB Line 869  static __forceinline void mmap_ClearCpuB
869  void mmap_PageFaultHandler::OnPageFaultEvent( const PageFaultInfo& info, bool& handled )  void mmap_PageFaultHandler::OnPageFaultEvent( const PageFaultInfo& info, bool& handled )
870  {  {
871          // get bad virtual address          // get bad virtual address
872          uptr offset = info.addr - (uptr)psM;          uptr offset = info.addr - (uptr)eeMem->Main;
873          if( offset >= Ps2MemSize::Base ) return;          if( offset >= Ps2MemSize::Base ) return;
874    
875          mmap_ClearCpuBlock( offset );          mmap_ClearCpuBlock( offset );
# Line 961  void mmap_PageFaultHandler::OnPageFaultE Line 879  void mmap_PageFaultHandler::OnPageFaultE
879  // Clears all block tracking statuses, manual protection flags, and write protection.  // Clears all block tracking statuses, manual protection flags, and write protection.
880  // This does not clear any recompiler blocks.  It is assumed (and necessary) for the caller  // This does not clear any recompiler blocks.  It is assumed (and necessary) for the caller
881  // to ensure the EErec is also reset in conjunction with calling this function.  // to ensure the EErec is also reset in conjunction with calling this function.
882    //  (this function is called by default from the eerecReset).
883  void mmap_ResetBlockTracking()  void mmap_ResetBlockTracking()
884  {  {
885          DevCon.WriteLn( "vtlb/mmap: Block Tracking reset..." );          //DbgCon.WriteLn( "vtlb/mmap: Block Tracking reset..." );
886          memzero( m_PageProtectInfo );          memzero( m_PageProtectInfo );
887          HostSys::MemProtect( psM, Ps2MemSize::Base, Protect_ReadWrite );          HostSys::MemProtect( eeMem->Main, Ps2MemSize::Base, Protect_ReadWrite );
888  }  }

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