/[pcsx2_0.9.7]/trunk/pcsx2/IopHw.h
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Contents of /trunk/pcsx2/IopHw.h

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Revision 273 - (show annotations) (download)
Fri Nov 12 01:10:22 2010 UTC (9 years, 7 months ago) by william
File MIME type: text/plain
File size: 9652 byte(s)
Auto Commited Import of: pcsx2-0.9.7-DEBUG (upstream: v0.9.7.4013 local: v0.9.7.197-latest) in ./trunk
1 /* PCSX2 - PS2 Emulator for PCs
2 * Copyright (C) 2002-2010 PCSX2 Dev Team
3 *
4 * PCSX2 is free software: you can redistribute it and/or modify it under the terms
5 * of the GNU Lesser General Public License as published by the Free Software Found-
6 * ation, either version 3 of the License, or (at your option) any later version.
7 *
8 * PCSX2 is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
9 * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
10 * PURPOSE. See the GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License along with PCSX2.
13 * If not, see <http://www.gnu.org/licenses/>.
14 */
15
16 #pragma once
17
18 #include "IopMem.h"
19
20 static const u32
21 HW_USB_START = 0x1f801600,
22 HW_USB_END = 0x1f801700,
23 HW_FW_START = 0x1f808400,
24 HW_FW_END = 0x1f808550, // end addr for FW is a guess...
25 HW_SPU2_START = 0x1f801c00,
26 HW_SPU2_END = 0x1f801e00;
27
28 static const u32
29 HW_SSBUS_SPD_ADDR = 0x1f801000,
30 HW_SSBUS_PIO_ADDR = 0x1f801004,
31 HW_SSBUS_SPD_DELAY = 0x1f801008,
32 HW_SSBUS_DEV1_DELAY = 0x1f80100C,
33 HW_SSBUS_ROM_DELAY = 0x1f801010,
34 HW_SSBUS_SPU_DELAY = 0x1f801014,
35 HW_SSBUS_DEV5_DELAY = 0x1f801018,
36 HW_SSBUS_PIO_DELAY = 0x1f80101c,
37 HW_SSBUS_COM_DELAY = 0x1f801020,
38
39 HW_SIO_DATA = 0x1f801040, // SIO read/write register
40 HW_SIO_STAT = 0x1f801044,
41 HW_SIO_MODE = 0x1f801048,
42 HW_SIO_CTRL = 0x1f80104a,
43 HW_SIO_BAUD = 0x1f80104e,
44
45 HW_RAM_SIZE = 0x1f801060,
46 HW_IREG = 0x1f801070,
47 HW_IMASK = 0x1f801074,
48 HW_ICTRL = 0x1f801078,
49
50 HW_SSBUS_DEV1_ADDR = 0x1f801400,
51 HW_SSBUS_SPU_ADDR = 0x1f801404,
52 HW_SSBUS_DEV5_ADDR = 0x1f801408,
53 HW_SSBUS_SPU1_ADDR = 0x1f80140c,
54 HW_SSBUS_DEV9_ADDR3 = 0x1f801410,
55 HW_SSBUS_SPU1_DELAY = 0x1f801414,
56 HW_SSBUS_DEV9_DELAY2= 0x1f801418,
57 HW_SSBUS_DEV9_DELAY3= 0x1f80141c,
58 HW_SSBUS_DEV9_DELAY1= 0x1f801420,
59
60 HW_ICFG = 0x1f801450,
61 HW_DEV9_DATA = 0x1f80146e, // DEV9 read/write register
62
63 // CDRom registers are used for various command, status, and data stuff.
64
65 HW_CDR_DATA0 = 0x1f801800, // CDROM multipurpose data register 1
66 HW_CDR_DATA1 = 0x1f801801, // CDROM multipurpose data register 2
67 HW_CDR_DATA2 = 0x1f801802, // CDROM multipurpose data register 3
68 HW_CDR_DATA3 = 0x1f801803, // CDROM multipurpose data register 4
69
70 // SIO2 is a DMA interface for the SIO.
71
72 HW_SIO2_DATAIN = 0x1F808260,
73 HW_SIO2_FIFO = 0x1f808264,
74 HW_SIO2_CTRL = 0x1f808268,
75 HW_SIO2_RECV1 = 0x1f80826c,
76 HW_SIO2_RECV2 = 0x1f808270,
77 HW_SIO2_RECV3 = 0x1f808274,
78 HW_SIO2_8278 = 0x1F808278, // May as well add defs
79 HW_SIO2_827C = 0x1F80827C, // for these 2...
80 HW_SIO2_INTR = 0x1f808280;
81
82 enum DMAMadrAddresses
83 {
84 HWx_DMA0_MADR = 0x1f801080,
85 HWx_DMA1_MADR = 0x1f801090,
86 HWx_DMA2_MADR = 0x1f8010a0,
87 HWx_DMA3_MADR = 0x1f8010b0,
88 HWx_DMA4_MADR = 0x1f8010c0,
89 HWx_DMA5_MADR = 0x1f8010d0,
90 HWx_DMA6_MADR = 0x1f8010e0,
91 HWx_DMA7_MADR = 0x1f801500,
92 HWx_DMA8_MADR = 0x1f801510,
93 HWx_DMA9_MADR = 0x1f801520,
94 HWx_DMA10_MADR = 0x1f801530,
95 HWx_DMA11_MADR = 0x1f801540,
96 HWx_DMA12_MADR = 0x1f801550
97 };
98
99 enum DMABcrAddresses
100 {
101 HWx_DMA0_BCR = 0x1f801084,
102 HWx_DMA1_BCR = 0x1f801094,
103 HWx_DMA2_BCR = 0x1f8010a4,
104 HWx_DMA3_BCR = 0x1f8010b4,
105 HWx_DMA3_BCR_L16 = 0x1f8010b4,
106 HWx_DMA3_BCR_H16 = 0x1f8010b6,
107 HWx_DMA4_BCR = 0x1f8010c4,
108 HWx_DMA5_BCR = 0x1f8010d4,
109 HWx_DMA6_BCR = 0x1f8010e4,
110 HWx_DMA7_BCR = 0x1f801504,
111 HWx_DMA8_BCR = 0x1f801514,
112 HWx_DMA9_BCR = 0x1f801524,
113 HWx_DMA10_BCR = 0x1f801534,
114 HWx_DMA11_BCR = 0x1f801544,
115 HWx_DMA12_BCR = 0x1f801554
116 };
117
118 enum DMAChcrAddresses
119 {
120 HWx_DMA0_CHCR = 0x1f801088,
121 HWx_DMA1_CHCR = 0x1f801098,
122 HWx_DMA2_CHCR = 0x1f8010a8,
123 HWx_DMA3_CHCR = 0x1f8010b8,
124 HWx_DMA4_CHCR = 0x1f8010c8,
125 HWx_DMA5_CHCR = 0x1f8010d8,
126 HWx_DMA6_CHCR = 0x1f8010e8,
127 HWx_DMA7_CHCR = 0x1f801508,
128 HWx_DMA8_CHCR = 0x1f801518,
129 HWx_DMA9_CHCR = 0x1f801528,
130 HWx_DMA10_CHCR = 0x1f801538,
131 HWx_DMA11_CHCR = 0x1f801548,
132 HWx_DMA12_CHCR = 0x1f801558
133 };
134
135 enum DMATadrAddresses
136 {
137 HWx_DMA0_TADR = 0x1f80108c,
138 HWx_DMA1_TADR = 0x1f80109c,
139 HWx_DMA2_TADR = 0x1f8010ac,
140 HWx_DMA3_TADR = 0x1f8010bc,
141 HWx_DMA4_TADR = 0x1f8010cc,
142 HWx_DMA5_TADR = 0x1f8010dc,
143 HWx_DMA6_TADR = 0x1f8010ec,
144 HWx_DMA7_TADR = 0x1f80150c,
145 HWx_DMA8_TADR = 0x1f80151c,
146 HWx_DMA9_TADR = 0x1f80152c,
147 HWx_DMA10_TADR = 0x1f80153c,
148 HWx_DMA11_TADR = 0x1f80154c,
149 HWx_DMA12_TADR = 0x1f80155c
150 };
151
152 /* Registers for the IOP Counters */
153 enum IOPCountRegs
154 {
155 IOP_T0_COUNT = 0x1f801100,
156 IOP_T1_COUNT = 0x1f801110,
157 IOP_T2_COUNT = 0x1f801120,
158 IOP_T3_COUNT = 0x1f801480,
159 IOP_T4_COUNT = 0x1f801490,
160 IOP_T5_COUNT = 0x1f8014a0,
161
162 IOP_T0_MODE = 0x1f801104,
163 IOP_T1_MODE = 0x1f801114,
164 IOP_T2_MODE = 0x1f801124,
165 IOP_T3_MODE = 0x1f801484,
166 IOP_T4_MODE = 0x1f801494,
167 IOP_T5_MODE = 0x1f8014a4,
168
169 IOP_T0_TARGET = 0x1f801108,
170 IOP_T1_TARGET = 0x1f801118,
171 IOP_T2_TARGET = 0x1f801128,
172 IOP_T3_TARGET = 0x1f801488,
173 IOP_T4_TARGET = 0x1f801498,
174 IOP_T5_TARGET = 0x1f8014a8
175 };
176
177 // fixme: I'm sure there's a better way to do this. --arcum42
178 #define DmaExec(n) { \
179 if (HW_DMA##n##_CHCR & 0x01000000 && \
180 HW_DMA_PCR & (8 << (n * 4))) { \
181 psxDma##n(HW_DMA##n##_MADR, HW_DMA##n##_BCR, HW_DMA##n##_CHCR); \
182 } \
183 }
184
185 #define DmaExec2(n) { \
186 if (HW_DMA##n##_CHCR & 0x01000000 && \
187 HW_DMA_PCR2 & (8 << ((n-7) * 4))) { \
188 psxDma##n(HW_DMA##n##_MADR, HW_DMA##n##_BCR, HW_DMA##n##_CHCR); \
189 } \
190 }
191
192 #ifdef ENABLE_NEW_IOPDMA
193 #define DmaExecNew(n) IopDmaStart(n);
194 #define DmaExecNew2(n) IopDmaStart(n);
195 #endif
196
197 struct dma_mbc
198 {
199 u32 madr;
200 u32 bcr;
201 u32 chcr;
202
203 u16 bcr_lower() const
204 {
205 return (u16)(bcr);
206 }
207 u16 bcr_upper() const
208 {
209 return (bcr >> 16);
210 }
211 wxString desc() const { return wxsFormat(L"madr: 0x%x bcr: 0x%x chcr: 0x%x", madr, bcr, chcr); }
212 };
213
214 struct dma_mbct
215 {
216 u32 madr;
217 u32 bcr;
218 u32 chcr;
219 u32 tadr;
220
221 u16 bcr_lower() const
222 {
223 return (u16)(bcr);
224 }
225 u16 bcr_upper() const
226 {
227 return (bcr >> 16);
228 }
229 wxString desc() const { return wxsFormat(L"madr: 0x%x bcr: 0x%x chcr: 0x%x tadr: 0x%x", madr, bcr, chcr, tadr); }
230 };
231
232 static dma_mbc& hw_dma0 = (dma_mbc&) iopHw[0x1080];
233 static dma_mbc& hw_dma1 = (dma_mbc&) iopHw[0x1090];
234 static dma_mbct& hw_dma2 = (dma_mbct&)iopHw[0x10a0];
235 static dma_mbc& hw_dma3 = (dma_mbc&) iopHw[0x10b0];
236 static dma_mbct& hw_dma4 = (dma_mbct&)iopHw[0x10c0];
237 static dma_mbc& hw_dma6 = (dma_mbc&) iopHw[0x10e0];
238 static dma_mbc& hw_dma7 = (dma_mbc&) iopHw[0x1500];
239 static dma_mbc& hw_dma8 = (dma_mbc&) iopHw[0x1510];
240 static dma_mbct& hw_dma9 = (dma_mbct&)iopHw[0x1520];
241 static dma_mbc& hw_dma10 = (dma_mbc&) iopHw[0x1530];
242 static dma_mbc& hw_dma11 = (dma_mbc&) iopHw[0x1540];
243 static dma_mbc& hw_dma12 = (dma_mbc&) iopHw[0x1550];
244
245 #define hw_dma(x) hw_dma##x
246
247 #define HW_DMA0_MADR (psxHu32(0x1080)) // MDEC in DMA
248 #define HW_DMA0_BCR (psxHu32(0x1084))
249 #define HW_DMA0_CHCR (psxHu32(0x1088))
250
251 #define HW_DMA1_MADR (psxHu32(0x1090)) // MDEC out DMA
252 #define HW_DMA1_BCR (psxHu32(0x1094))
253 #define HW_DMA1_CHCR (psxHu32(0x1098))
254
255 #define HW_DMA2_MADR (psxHu32(0x10a0)) // GPU DMA
256 #define HW_DMA2_BCR (psxHu32(0x10a4))
257 #define HW_DMA2_CHCR (psxHu32(0x10a8))
258 #define HW_DMA2_TADR (psxHu32(0x10ac))
259
260 #define HW_DMA3_MADR (psxHu32(0x10b0)) // CDROM DMA
261 #define HW_DMA3_BCR (psxHu32(0x10b4))
262 #define HW_DMA3_BCR_L16 (psxHu16(0x10b4))
263 #define HW_DMA3_BCR_H16 (psxHu16(0x10b6))
264 #define HW_DMA3_CHCR (psxHu32(0x10b8))
265
266 #define HW_DMA4_MADR (psxHu32(0x10c0)) // SPU DMA
267 #define HW_DMA4_BCR (psxHu32(0x10c4))
268 #define HW_DMA4_CHCR (psxHu32(0x10c8))
269 #define HW_DMA4_TADR (psxHu32(0x10cc))
270
271 #define HW_DMA6_MADR (psxHu32(0x10e0)) // GPU DMA (OT)
272 #define HW_DMA6_BCR (psxHu32(0x10e4))
273 #define HW_DMA6_CHCR (psxHu32(0x10e8))
274
275 #define HW_DMA7_MADR (psxHu32(0x1500)) // SPU2 DMA
276 #define HW_DMA7_BCR (psxHu32(0x1504))
277 #define HW_DMA7_CHCR (psxHu32(0x1508))
278
279 #define HW_DMA8_MADR (psxHu32(0x1510)) // DEV9 DMA
280 #define HW_DMA8_BCR (psxHu32(0x1514))
281 #define HW_DMA8_CHCR (psxHu32(0x1518))
282
283 #define HW_DMA9_MADR (psxHu32(0x1520)) // SIF0 DMA
284 #define HW_DMA9_BCR (psxHu32(0x1524))
285 #define HW_DMA9_CHCR (psxHu32(0x1528))
286 #define HW_DMA9_TADR (psxHu32(0x152c))
287
288 #define HW_DMA10_MADR (psxHu32(0x1530)) // SIF1 DMA
289 #define HW_DMA10_BCR (psxHu32(0x1534))
290 #define HW_DMA10_CHCR (psxHu32(0x1538))
291
292 #define HW_DMA11_MADR (psxHu32(0x1540)) // SIO2 in
293 #define HW_DMA11_BCR (psxHu32(0x1544))
294 #define HW_DMA11_CHCR (psxHu32(0x1548))
295
296 #define HW_DMA12_MADR (psxHu32(0x1550)) // SIO2 out
297 #define HW_DMA12_BCR (psxHu32(0x1554))
298 #define HW_DMA12_CHCR (psxHu32(0x1558))
299
300 #define HW_DMA_PCR (psxHu32(0x10f0))
301 #define HW_DMA_ICR (psxHu32(0x10f4))
302
303 #define HW_DMA_PCR2 (psxHu32(0x1570))
304 #define HW_DMA_ICR2 (psxHu32(0x1574))
305
306 enum IopEventId
307 {
308 IopEvt_SIFhack = 1 // The SIF likes to fall asleep and never wake up. This sends intermittent SBUS flags to rewake it.
309 , IopEvt_Cdvd = 5 // General Cdvd commands (Seek, Standby, Break, etc)
310 , IopEvt_SIF0 = 9
311 , IopEvt_SIF1 = 10
312 , IopEvt_Dma11 = 11
313 , IopEvt_Dma12 = 12
314 , IopEvt_SIO = 16
315 , IopEvt_Cdrom = 17
316 , IopEvt_CdromRead = 18
317 , IopEvt_CdvdRead = 19
318 , IopEvt_DEV9 = 20
319 , IopEvt_USB = 21
320 };
321
322 extern void PSX_INT( IopEventId n, s32 ecycle);
323
324 extern void psxSetNextBranch( u32 startCycle, s32 delta );
325 extern void psxSetNextBranchDelta( s32 delta );
326 extern int iopTestCycle( u32 startCycle, s32 delta );
327 extern void _iopTestInterrupts();
328
329 extern void psxHwReset();
330 extern u8 psxHw4Read8 (u32 add);
331 extern void psxHw4Write8(u32 add, u8 value);
332
333 extern void psxDmaInterrupt(int n);
334 extern void psxDmaInterrupt2(int n);

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