/[pcsx2_0.9.7]/trunk/pcsx2/IopDma.cpp
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Contents of /trunk/pcsx2/IopDma.cpp

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Revision 273 - (show annotations) (download)
Fri Nov 12 01:10:22 2010 UTC (9 years, 3 months ago) by william
File size: 18185 byte(s)
Auto Commited Import of: pcsx2-0.9.7-DEBUG (upstream: v0.9.7.4013 local: v0.9.7.197-latest) in ./trunk
1 /* PCSX2 - PS2 Emulator for PCs
2 * Copyright (C) 2002-2010 PCSX2 Dev Team
3 *
4 * PCSX2 is free software: you can redistribute it and/or modify it under the terms
5 * of the GNU Lesser General Public License as published by the Free Software Found-
6 * ation, either version 3 of the License, or (at your option) any later version.
7 *
8 * PCSX2 is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
9 * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
10 * PURPOSE. See the GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License along with PCSX2.
13 * If not, see <http://www.gnu.org/licenses/>.
14 */
15
16 #include "PrecompiledHeader.h"
17 #include "IopCommon.h"
18
19 #include "Sif.h"
20
21 using namespace R3000A;
22
23 // Dma0/1 in Mdec.c
24 // Dma3 in CdRom.c
25 // Dma8 in PsxSpd.c
26 // Dma11/12 in PsxSio2.c
27
28 #ifndef ENABLE_NEW_IOPDMA_SPU2
29 static void __fastcall psxDmaGeneric(u32 madr, u32 bcr, u32 chcr, u32 spuCore, _SPU2writeDMA4Mem spu2WriteFunc, _SPU2readDMA4Mem spu2ReadFunc)
30 {
31 const char dmaNum = spuCore ? '7' : '4';
32
33 /*if (chcr & 0x400) DevCon.Status("SPU 2 DMA %c linked list chain mode! chcr = %x madr = %x bcr = %x\n", dmaNum, chcr, madr, bcr);
34 if (chcr & 0x40000000) DevCon.Warning("SPU 2 DMA %c Unusual bit set on 'to' direction chcr = %x madr = %x bcr = %x\n", dmaNum, chcr, madr, bcr);
35 if ((chcr & 0x1) == 0) DevCon.Status("SPU 2 DMA %c loading from spu2 memory chcr = %x madr = %x bcr = %x\n", dmaNum, chcr, madr, bcr);*/
36
37 const int size = (bcr >> 16) * (bcr & 0xFFFF);
38
39 // Update the spu2 to the current cycle before initiating the DMA
40
41 if (SPU2async)
42 {
43 SPU2async(psxRegs.cycle - psxCounters[6].sCycleT);
44 //Console.Status("cycles sent to SPU2 %x\n", psxRegs.cycle - psxCounters[6].sCycleT);
45
46 psxCounters[6].sCycleT = psxRegs.cycle;
47 psxCounters[6].CycleT = size * 3;
48
49 psxNextCounter -= (psxRegs.cycle - psxNextsCounter);
50 psxNextsCounter = psxRegs.cycle;
51 if (psxCounters[6].CycleT < psxNextCounter)
52 psxNextCounter = psxCounters[6].CycleT;
53
54 if((g_iopNextEventCycle - psxNextsCounter) > (u32)psxNextCounter)
55 {
56 //DevCon.Warning("SPU2async Setting new counter branch, old %x new %x ((%x - %x = %x) > %x delta)", g_iopNextEventCycle, psxNextsCounter + psxNextCounter, g_iopNextEventCycle, psxNextsCounter, (g_iopNextEventCycle - psxNextsCounter), psxNextCounter);
57 g_iopNextEventCycle = psxNextsCounter + psxNextCounter;
58 }
59 }
60
61 switch (chcr)
62 {
63 case 0x01000201: //cpu to spu2 transfer
64 PSXDMA_LOG("*** DMA %c - mem2spu *** %x addr = %x size = %x", dmaNum, chcr, madr, bcr);
65 spu2WriteFunc((u16 *)iopPhysMem(madr), size*2);
66 break;
67
68 case 0x01000200: //spu2 to cpu transfer
69 PSXDMA_LOG("*** DMA %c - spu2mem *** %x addr = %x size = %x", dmaNum, chcr, madr, bcr);
70 spu2ReadFunc((u16 *)iopPhysMem(madr), size*2);
71 psxCpu->Clear(spuCore ? HW_DMA7_MADR : HW_DMA4_MADR, size);
72 break;
73
74 default:
75 Console.Error("*** DMA %c - SPU unknown *** %x addr = %x size = %x", dmaNum, chcr, madr, bcr);
76 break;
77 }
78 }
79
80 void psxDma4(u32 madr, u32 bcr, u32 chcr) // SPU2's Core 0
81 {
82 psxDmaGeneric(madr, bcr, chcr, 0, SPU2writeDMA4Mem, SPU2readDMA4Mem);
83 }
84
85 int psxDma4Interrupt()
86 {
87 #ifdef SPU2IRQTEST
88 Console.Warning("psxDma4Interrupt()");
89 #endif
90 HW_DMA4_CHCR &= ~0x01000000;
91 psxDmaInterrupt(4);
92 iopIntcIrq(9);
93 return 1;
94 }
95
96 void spu2DMA4Irq()
97 {
98 #ifdef SPU2IRQTEST
99 Console.Warning("spu2DMA4Irq()");
100 #endif
101 SPU2interruptDMA4();
102 HW_DMA4_CHCR &= ~0x01000000;
103 psxDmaInterrupt(4);
104 }
105
106 void psxDma7(u32 madr, u32 bcr, u32 chcr) // SPU2's Core 1
107 {
108 psxDmaGeneric(madr, bcr, chcr, 1, SPU2writeDMA7Mem, SPU2readDMA7Mem);
109 }
110
111 int psxDma7Interrupt()
112 {
113 #ifdef SPU2IRQTEST
114 Console.Warning("psxDma7Interrupt()");
115 #endif
116 HW_DMA7_CHCR &= ~0x01000000;
117 psxDmaInterrupt2(0);
118 return 1;
119
120 }
121
122 void spu2DMA7Irq()
123 {
124 #ifdef SPU2IRQTEST
125 Console.Warning("spu2DMA7Irq()");
126 #endif
127 SPU2interruptDMA7();
128 HW_DMA7_CHCR &= ~0x01000000;
129 psxDmaInterrupt2(0);
130 }
131
132 #endif
133
134 #ifndef DISABLE_PSX_GPU_DMAS
135 void psxDma2(u32 madr, u32 bcr, u32 chcr) // GPU
136 {
137 HW_DMA2_CHCR &= ~0x01000000;
138 psxDmaInterrupt(2);
139 }
140
141 void psxDma6(u32 madr, u32 bcr, u32 chcr)
142 {
143 u32 *mem = (u32 *)iopPhysMem(madr);
144
145 PSXDMA_LOG("*** DMA 6 - OT *** %lx addr = %lx size = %lx", chcr, madr, bcr);
146
147 if (chcr == 0x11000002)
148 {
149 while (bcr--)
150 {
151 *mem-- = (madr - 4) & 0xffffff;
152 madr -= 4;
153 }
154 mem++;
155 *mem = 0xffffff;
156 }
157 else
158 {
159 // Unknown option
160 PSXDMA_LOG("*** DMA 6 - OT unknown *** %lx addr = %lx size = %lx", chcr, madr, bcr);
161 }
162 HW_DMA6_CHCR &= ~0x01000000;
163 psxDmaInterrupt(6);
164 }
165 #endif
166
167 #ifndef ENABLE_NEW_IOPDMA_DEV9
168 void psxDma8(u32 madr, u32 bcr, u32 chcr)
169 {
170 const int size = (bcr >> 16) * (bcr & 0xFFFF) * 8;
171
172 switch (chcr & 0x01000201)
173 {
174 case 0x01000201: //cpu to dev9 transfer
175 PSXDMA_LOG("*** DMA 8 - DEV9 mem2dev9 *** %lx addr = %lx size = %lx", chcr, madr, bcr);
176 DEV9writeDMA8Mem((u32*)iopPhysMem(madr), size);
177 break;
178
179 case 0x01000200: //dev9 to cpu transfer
180 PSXDMA_LOG("*** DMA 8 - DEV9 dev9mem *** %lx addr = %lx size = %lx", chcr, madr, bcr);
181 DEV9readDMA8Mem((u32*)iopPhysMem(madr), size);
182 break;
183
184 default:
185 PSXDMA_LOG("*** DMA 8 - DEV9 unknown *** %lx addr = %lx size = %lx", chcr, madr, bcr);
186 break;
187 }
188 HW_DMA8_CHCR &= ~0x01000000;
189 psxDmaInterrupt2(1);
190 }
191 #endif
192
193 void psxDma9(u32 madr, u32 bcr, u32 chcr)
194 {
195 SIF_LOG("IOP: dmaSIF0 chcr = %lx, madr = %lx, bcr = %lx, tadr = %lx", chcr, madr, bcr, HW_DMA9_TADR);
196
197 sif0.iop.busy = true;
198
199 SIF0Dma();
200 }
201
202 void psxDma10(u32 madr, u32 bcr, u32 chcr)
203 {
204 SIF_LOG("IOP: dmaSIF1 chcr = %lx, madr = %lx, bcr = %lx", chcr, madr, bcr);
205
206 sif1.iop.busy = true;
207
208 SIF1Dma();
209 }
210
211 /* psxDma11 & psxDma 12 are in IopSio2.cpp, along with the appropriate interrupt functions. */
212
213 //////////////////////////////////////////////////////////////////////////////////////////////
214 //
215 // Gigaherz's "Improved DMA Handling" Engine WIP...
216 //
217
218 #ifdef ENABLE_NEW_IOPDMA
219
220 //////////////////////////////////////////////////////////////////////////////////////////////
221 // Local Declarations
222
223 // in IopSio2.cpp
224 extern s32 CALLBACK sio2DmaStart(s32 channel, u32 madr, u32 bcr, u32 chcr);
225 extern s32 CALLBACK sio2DmaRead(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed);
226 extern s32 CALLBACK sio2DmaWrite(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed);
227 extern void CALLBACK sio2DmaInterrupt(s32 channel);
228
229 // implemented below
230 s32 CALLBACK errDmaWrite(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed);
231 s32 CALLBACK errDmaRead(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed);
232
233 // pointer types
234 typedef s32 (CALLBACK * DmaHandler)(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed);
235 typedef void (CALLBACK * DmaIHandler)(s32 channel);
236 typedef s32 (CALLBACK * DmaSHandler)(s32 channel, u32 madr, u32 bcr, u32 chcr);
237
238 // constants
239 struct DmaHandlerInfo
240 {
241 const char* Name;
242
243 // doubles as a "disable" flag
244 u32 DirectionFlags;
245 u32 DmacRegisterBase;
246 DmaHandler Read;
247 DmaHandler Write;
248 DmaIHandler Interrupt;
249 DmaSHandler Start;
250
251 __fi u32& REG_MADR(void) const { return psxHu32(DmacRegisterBase + 0x0); }
252 __fi u32& REG_BCR(void) const { return psxHu32(DmacRegisterBase + 0x4); }
253 __fi u32& REG_CHCR(void) const { return psxHu32(DmacRegisterBase + 0x8); }
254 __fi u32& REG_TADR(void) const { return psxHu32(DmacRegisterBase + 0xC); }
255 };
256
257 #define MEM_BASE1 0x1f801080
258 #define MEM_BASE2 0x1f801500
259
260 #define CHANNEL_BASE1(ch) (MEM_BASE1 + ((ch)<<4))
261 #define CHANNEL_BASE2(ch) (MEM_BASE2 + ((ch)<<4))
262
263 // channel disabled
264 #define _D__ 0
265 #define _D_W 1
266 #define _DR_ 2
267 #define _DRW 3
268 // channel enabled
269 #define _E__ 4
270 #define _E_W 5
271 #define _ER_ 6
272 #define _ERW 7
273
274 //////////////////////////////////////////////////////////////////////////////////////////////
275 // Plugin interface accessors
276
277 #ifdef ENABLE_NEW_IOPDMA_SPU2
278 s32 CALLBACK spu2DmaRead (s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed) { return SPU2dmaRead(channel,data,bytesLeft,bytesProcessed); }
279 s32 CALLBACK spu2DmaWrite (s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed) { return SPU2dmaWrite(channel,data,bytesLeft,bytesProcessed); }
280 void CALLBACK spu2DmaInterrupt (s32 channel) { SPU2dmaInterrupt(channel); }
281 #else
282 s32 CALLBACK spu2DmaRead (s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed) { *bytesProcessed=0; return 0; }
283 s32 CALLBACK spu2DmaWrite (s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed) { *bytesProcessed=0; return 0; }
284 void CALLBACK spu2DmaInterrupt (s32 channel) { }
285 #endif
286 #ifdef ENABLE_NEW_IOPDMA_DEV9
287 s32 CALLBACK dev9DmaRead (s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed) { return DEV9dmaRead(channel,data,bytesLeft,bytesProcessed); }
288 s32 CALLBACK dev9DmaWrite (s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed) { return DEV9dmaWrite(channel,data,bytesLeft,bytesProcessed); }
289 void CALLBACK dev9DmaInterrupt (s32 channel) { DEV9dmaInterrupt(channel); }
290 #else
291 s32 CALLBACK dev9DmaRead (s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed) { *bytesProcessed=0; return 0; }
292 s32 CALLBACK dev9DmaWrite (s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed) { *bytesProcessed=0; return 0; }
293 void CALLBACK dev9DmaInterrupt (s32 channel) { }
294 #endif
295
296 //////////////////////////////////////////////////////////////////////////////////////////////
297 // Dma channel definitions
298
299 const DmaHandlerInfo IopDmaHandlers[DMA_CHANNEL_MAX] =
300 {
301 // First DMAC, same as PS1
302 {"Ps1 Mdec in", _D__}, //0
303 {"Ps1 Mdec out", _D__}, //1
304 {"Ps1 Gpu", _D__}, //2
305 #ifdef ENABLE_NEW_IOPDMA_CDVD
306 {"CDVD", _ER_, CHANNEL_BASE1(3), cdvdDmaRead, errDmaWrite, cdvdDmaInterrupt}, //3: CDVD
307 #else
308 {"CDVD", _D__}, //3: CDVD
309 #endif
310 #ifdef ENABLE_NEW_IOPDMA_SPU2
311 {"SPU2 Core0", _ERW, CHANNEL_BASE1(4), spu2DmaRead, spu2DmaWrite, spu2DmaInterrupt}, //4: Spu/Spu2 Core0
312 #else
313 {"SPU2 Core0", _D__}, //4: Spu/Spu2 Core0
314 #endif
315 {"Ps1 PIO", _D__}, //5: PIO
316 {"Ps1 OTC", _D__}, //6: "reverse clear OT" - PSX GPU related
317
318 // Second DMAC, new in PS2 IOP
319 #ifdef ENABLE_NEW_IOPDMA_SPU2
320 {"SPU2 Core1", _ERW, CHANNEL_BASE2(0), spu2DmaRead, spu2DmaWrite, spu2DmaInterrupt}, //7: Spu2 Core1
321 #else
322 {"SPU2 Core1", _D__}, //7: Spu2 Core1
323 #endif
324 #ifdef ENABLE_NEW_IOPDMA_DEV9
325 {"Dev9", _ERW, CHANNEL_BASE2(1), dev9DmaRead, dev9DmaWrite, dev9DmaInterrupt}, //8: Dev9
326 #else
327 {"Dev9", _D__}, //8: Dev9
328 #endif
329 #ifdef ENABLE_NEW_IOPDMA_SIF
330 {"Sif0", _ERW, CHANNEL_BASE2(2), sif0DmaRead, sif0DmaWrite, sif0DmaInterrupt}, //9: SIF0
331 {"Sif1", _ERW, CHANNEL_BASE2(3), sif1DmaRead, sif1DmaWrite, sif1DmaInterrupt}, //10: SIF1
332 #else
333 {"Sif0", _D__}, //9: SIF0
334 {"Sif1", _D__}, //10: SIF1
335 #endif
336 #ifdef ENABLE_NEW_IOPDMA_SIO
337 {"Sio2 (writes)", _E_W, CHANNEL_BASE2(4), errDmaRead, sio2DmaWrite, sio2DmaInterrupt, sio2DmaStart}, //11: Sio2
338 {"Sio2 (reads)", _ER_, CHANNEL_BASE2(5), sio2DmaRead, errDmaWrite, sio2DmaInterrupt, sio2DmaStart}, //12: Sio2
339 #else
340 {"Sio2 (writes)", _D__}, //11: Sio2
341 {"Sio2 (reads)", _D__}, //12: Sio2
342 #endif
343 {"?", _D__}, //13
344 // if each dmac has 7 channels, the list would end here, but I'm not sure :p
345 };
346
347 // runtime variables
348 struct DmaChannelInfo
349 {
350 s32 ByteCount;
351 s32 NextUpdate;
352 } IopDmaChannels[DMA_CHANNEL_MAX] = {0};
353
354
355 //////////////////////////////////////////////////////////////////////////////////////////////
356 // Tool functions
357 void SetDmaUpdateTarget(u32 delay)
358 {
359 psxCounters[8].CycleT = delay;
360 if (delay < psxNextCounter)
361 psxNextCounter = delay;
362 }
363
364 void RaiseDmaIrq(u32 channel)
365 {
366 if(channel<7)
367 psxDmaInterrupt(channel);
368 else
369 psxDmaInterrupt2(channel-7);
370 }
371
372 //////////////////////////////////////////////////////////////////////////////////////////////
373 // IopDmaStart: Called from IopHwWrite to test and possibly start a dma transfer
374
375 void IopDmaStart(int channel)
376 {
377 if(!(IopDmaHandlers[channel].DirectionFlags&_E__))
378 return;
379
380 int chcr = IopDmaHandlers[channel].REG_CHCR();
381
382 int pcr = (channel>=7)?(HW_DMA_PCR2 & (8 << ((channel-7) * 4))):(HW_DMA_PCR & (8 << (channel * 4)));
383
384 if ( !(chcr & 0x01000000) || !pcr)
385 return;
386
387 // I dont' really understand this, but it's used above. Is this BYTES OR WHAT?
388 int bcr = IopDmaHandlers[channel].REG_BCR();
389 int bcr_size = (bcr & 0xFFFF);
390 int bcr_count = (bcr >> 16);
391 int size = 4* bcr_count * bcr_size;
392
393 int dirf = IopDmaHandlers[channel].DirectionFlags&3;
394
395 if(dirf != 3)
396 {
397 bool ok = (chcr & DMA_CTRL_DIRECTION)? (dirf==_D_W) : (dirf==_DR_);
398 if(!ok)
399 {
400 // hack?!
401 IopDmaHandlers[channel].REG_CHCR() &= ~DMA_CTRL_ACTIVE;
402 return;
403 }
404 }
405
406 if(IopDmaHandlers[channel].Start)
407 {
408 int ret = IopDmaHandlers[channel].Start(channel,
409 IopDmaHandlers[channel].REG_MADR(),
410 IopDmaHandlers[channel].REG_BCR(),
411 IopDmaHandlers[channel].REG_CHCR());
412 if(ret < 0)
413 {
414 IopDmaHandlers[channel].REG_CHCR() &= ~DMA_CTRL_ACTIVE;
415 return;
416 }
417 }
418
419 //Console.WriteLn(Color_StrongOrange,"Starting NewDMA ch=%d, size=%d(0x%08x), dir=%d", channel, size, bcr, chcr&DMA_CTRL_DIRECTION);
420
421 IopDmaHandlers[channel].REG_CHCR() |= DMA_CTRL_ACTIVE;
422 IopDmaChannels[channel].ByteCount = size;
423 IopDmaChannels[channel].NextUpdate = 0;
424
425 //SetDmaUpdateTarget(1);
426 {
427 const s32 difference = psxRegs.cycle - psxCounters[8].sCycleT;
428
429 psxCounters[8].sCycleT = psxRegs.cycle;
430 psxCounters[8].CycleT = psxCounters[8].rate;
431 IopDmaUpdate(difference);
432
433 s32 c = psxCounters[8].CycleT;
434 if (c < psxNextCounter) psxNextCounter = c;
435 }
436 }
437
438 //////////////////////////////////////////////////////////////////////////////////////////////
439 // IopDmaProcessChannel: Called from IopDmaUpdate (below) to process a dma channel
440
441 template<int channel>
442 static void __ri IopDmaProcessChannel(int elapsed, int& MinDelay)
443 {
444 // Hopefully the compiler would be able to optimize the whole function away if this doesn't pass.
445 if(!(IopDmaHandlers[channel].DirectionFlags&_E__))
446 return;
447
448 DmaChannelInfo *ch = IopDmaChannels + channel;
449 const DmaHandlerInfo *hh = IopDmaHandlers + channel;
450
451 if (hh->REG_CHCR()&DMA_CTRL_ACTIVE)
452 {
453 ch->NextUpdate -= elapsed;
454 if (ch->NextUpdate <= 0) // Refresh target passed
455 {
456 if (ch->ByteCount <= 0) // No more data left, finish dma
457 {
458 ch->NextUpdate = 0x7fffffff;
459
460 hh->REG_CHCR() &= ~DMA_CTRL_ACTIVE;
461 RaiseDmaIrq(channel);
462 hh->Interrupt(channel);
463 }
464 else // let the handlers transfer more data
465 {
466 int chcr = hh->REG_CHCR();
467
468 DmaHandler handler = (chcr & DMA_CTRL_DIRECTION) ? hh->Write : hh->Read;
469
470 u32 ProcessedBytes = 0;
471 s32 RequestedDelay = (handler) ? handler(channel, (u32*)iopPhysMem(hh->REG_MADR()), ch->ByteCount, &ProcessedBytes) : 0;
472
473 if(ProcessedBytes>0 && (!(chcr & DMA_CTRL_DIRECTION)))
474 {
475 psxCpu->Clear(hh->REG_MADR(), ProcessedBytes/4);
476 }
477
478 int NextUpdateDelay = 100;
479 if (RequestedDelay < 0) // error code
480 {
481 // TODO: ... What to do if the handler gives an error code? :P
482 DevCon.Warning("ERROR on channel %d",channel);
483 hh->REG_CHCR() &= ~DMA_CTRL_ACTIVE;
484 RaiseDmaIrq(channel);
485 hh->Interrupt(channel);
486 }
487 else if (ProcessedBytes > 0) // if not an error, continue transfer
488 {
489 //DevCon.WriteLn("Transfer channel %d, ProcessedBytes = %d",i,ProcessedBytes);
490 hh->REG_MADR()+= ProcessedBytes;
491 ch->ByteCount -= ProcessedBytes;
492
493 NextUpdateDelay = ProcessedBytes/2; // / ch->Width;
494 }
495 else if(RequestedDelay==0)
496 DevCon.Warning("What now? :p"); // its ok as long as there's a delay requeste, autodma requires this.
497
498 if (RequestedDelay != 0) NextUpdateDelay = RequestedDelay;
499
500 // SPU2 adma early interrupts. PCSX2 likes those better currently.
501 if((channel==4 || channel==7) && (ch->ByteCount<=0) && (ProcessedBytes <= 1024))
502 {
503 ch->NextUpdate = 0;
504 }
505 else
506 ch->NextUpdate += NextUpdateDelay;
507
508 //ch->NextUpdate += NextUpdateDelay;
509 }
510 }
511
512 int nTarget = ch->NextUpdate;
513 if(nTarget < 0) nTarget = 0;
514
515 if (nTarget<MinDelay)
516 MinDelay = nTarget;
517 }
518 }
519
520 //////////////////////////////////////////////////////////////////////////////////////////////
521 // IopDmaProcessChannel: Called regularly to update the active channels
522
523 void IopDmaUpdate(u32 elapsed)
524 {
525 s32 MinDelay=0;
526
527 do {
528 MinDelay = 0x7FFFFFFF; // max possible value
529
530 // Unrolled
531 //IopDmaProcessChannel<0>(elapsed, MinDelay);
532 //IopDmaProcessChannel<1>(elapsed, MinDelay);
533 //IopDmaProcessChannel<2>(elapsed, MinDelay);
534 IopDmaProcessChannel<3>(elapsed, MinDelay);
535 IopDmaProcessChannel<4>(elapsed, MinDelay);
536 //IopDmaProcessChannel<5>(elapsed, MinDelay);
537 //IopDmaProcessChannel<6>(elapsed, MinDelay);
538 IopDmaProcessChannel<7>(elapsed, MinDelay);
539 IopDmaProcessChannel<8>(elapsed, MinDelay);
540 IopDmaProcessChannel<9>(elapsed, MinDelay);
541 IopDmaProcessChannel<10>(elapsed, MinDelay);
542 IopDmaProcessChannel<11>(elapsed, MinDelay);
543 IopDmaProcessChannel<12>(elapsed, MinDelay);
544 //IopDmaProcessChannel<13>(elapsed, MinDelay);
545
546 // reset elapsed time in case we loop
547 elapsed=0;
548 }
549 while(MinDelay <= 0);
550
551 if(MinDelay<0x7FFFFFFF)
552 {
553 // tell the iop when to call this function again
554 SetDmaUpdateTarget(MinDelay);
555 }
556 else
557 {
558 // bogus value so the function gets called again, not sure if it's necessary anymore
559 SetDmaUpdateTarget(10000);
560 }
561 }
562
563 //////////////////////////////////////////////////////////////////////////////////////////////
564 // Error functions: dummy functions for unsupported dma "directions"
565
566 s32 CALLBACK errDmaRead(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed)
567 {
568 Console.Error("ERROR: Tried to read using DMA %d (%s). Ignoring.", channel, IopDmaHandlers[channel]);
569
570 *bytesProcessed = bytesLeft;
571 return 0;
572 }
573
574 s32 CALLBACK errDmaWrite(s32 channel, u32* data, u32 bytesLeft, u32* bytesProcessed)
575 {
576 Console.Error("ERROR: Tried to write using DMA %d (%s). Ignoring.", channel, IopDmaHandlers[channel]);
577
578 *bytesProcessed = bytesLeft;
579 return 0;
580 }
581
582 void SaveStateBase::iopDmacFreeze()
583 {
584 FreezeTag("iopDmac");
585
586 Freeze(IopDmaChannels);
587
588 if( IsLoading() )
589 {
590 SetDmaUpdateTarget(10000); // Might be needed to kickstart the main updater :p
591 }
592 }
593
594 #endif

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