/[pcsx2_0.9.7]/trunk/pcsx2/IPU/IPU.h
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Contents of /trunk/pcsx2/IPU/IPU.h

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Revision 10 - (show annotations) (download)
Mon Sep 6 11:40:06 2010 UTC (9 years, 5 months ago) by william
File MIME type: text/plain
File size: 8744 byte(s)
exported r3113 from ./upstream/trunk
1 /* PCSX2 - PS2 Emulator for PCs
2 * Copyright (C) 2002-2010 PCSX2 Dev Team
3 *
4 * PCSX2 is free software: you can redistribute it and/or modify it under the terms
5 * of the GNU Lesser General Public License as published by the Free Software Found-
6 * ation, either version 3 of the License, or (at your option) any later version.
7 *
8 * PCSX2 is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
9 * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
10 * PURPOSE. See the GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License along with PCSX2.
13 * If not, see <http://www.gnu.org/licenses/>.
14 */
15
16 #ifndef __IPU_H__
17 #define __IPU_H__
18
19 #include "mpeg2lib/Mpeg.h"
20 #include "coroutine.h"
21 #include "IPU_Fifo.h"
22
23 #ifdef _MSC_VER
24 #pragma pack(1)
25 #endif
26
27 #define ipumsk( src ) ( (src) & 0xff )
28 #define ipucase( src ) case ipumsk(src)
29
30 #define IPU_INT_TO( cycles ) if(!(cpuRegs.interrupt & (1<<4))) CPU_INT( DMAC_TO_IPU, cycles )
31 #define IPU_INT_FROM( cycles ) CPU_INT( DMAC_FROM_IPU, cycles )
32
33 #define IPU_FORCEINLINE __forceinline
34
35 struct IPUStatus {
36 bool InProgress;
37 u8 DMAMode;
38 bool DMAFinished;
39 bool IRQTriggered;
40 u8 TagFollow;
41 u32 TagAddr;
42 bool stalled;
43 u8 ChainMode;
44 u32 NextMem;
45 };
46
47 #define DMA_MODE_NORMAL 0
48 #define DMA_MODE_CHAIN 1
49
50 #define IPU1_TAG_FOLLOW 0
51 #define IPU1_TAG_QWC 1
52 #define IPU1_TAG_ADDR 2
53 #define IPU1_TAG_NONE 3
54
55 //
56 // Bitfield Structures
57 //
58
59 struct tIPU_CMD
60 {
61 union
62 {
63 struct
64 {
65 u32 OPTION : 28; // VDEC decoded value
66 u32 CMD : 4; // last command
67 };
68 u32 DATA;
69 };
70 u32 BUSY;
71 };
72
73 union tIPU_CTRL {
74 struct {
75 u32 IFC : 4; // Input FIFO counter
76 u32 OFC : 4; // Output FIFO counter
77 u32 CBP : 6; // Coded block pattern
78 u32 ECD : 1; // Error code pattern
79 u32 SCD : 1; // Start code detected
80 u32 IDP : 2; // Intra DC precision
81 u32 resv0 : 2;
82 u32 AS : 1; // Alternate scan
83 u32 IVF : 1; // Intra VLC format
84 u32 QST : 1; // Q scale step
85 u32 MP1 : 1; // MPEG1 bit stream
86 u32 PCT : 3; // Picture Type
87 u32 resv1 : 3;
88 u32 RST : 1; // Reset
89 u32 BUSY : 1; // Busy
90 };
91 u32 _u32;
92
93 tIPU_CTRL( u32 val ) { _u32 = val; }
94
95 // CTRL = the first 16 bits of ctrl [0x8000ffff], + value for the next 16 bits,
96 // minus the reserved bits. (18-19; 27-29) [0x47f30000]
97 void write(u32 value) { _u32 = (value & 0x47f30000) | (_u32 & 0x8000ffff); }
98
99 bool test(u32 flags) const { return !!(_u32 & flags); }
100 void set_flags(u32 flags) { _u32 |= flags; }
101 void clear_flags(u32 flags) { _u32 &= ~flags; }
102 void reset() { _u32 = 0; }
103 };
104
105 struct tIPU_BP {
106 u32 BP; // Bit stream point
107 u16 IFC; // Input FIFO counter
108 u8 FP; // FIFO point
109 u8 bufferhasnew; // Always 0.
110 wxString desc() const
111 {
112 return wxsFormat(L"Ipu BP: bp = 0x%x, IFC = 0x%x, FP = 0x%x.", BP, IFC, FP);
113 }
114 };
115
116 #ifdef _WIN32
117 #pragma pack()
118 #endif
119
120 union tIPU_CMD_IDEC
121 {
122 struct
123 {
124 u32 FB : 6;
125 u32 UN2 :10;
126 u32 QSC : 5;
127 u32 UN1 : 3;
128 u32 DTD : 1;
129 u32 SGN : 1;
130 u32 DTE : 1;
131 u32 OFM : 1;
132 u32 cmd : 4;
133 };
134
135 u32 _u32;
136
137 tIPU_CMD_IDEC( u32 val ) { _u32 = val; }
138
139 bool test(u32 flags) const { return !!(_u32 & flags); }
140 void set_flags(u32 flags) { _u32 |= flags; }
141 void clear_flags(u32 flags) { _u32 &= ~flags; }
142 void reset() { _u32 = 0; }
143 void log()
144 {
145 IPU_LOG("IPU IDEC command.");
146
147 if (FB) IPU_LOG(" Skip %d bits.", FB);
148 IPU_LOG(" Quantizer step code=0x%X.", QSC);
149
150 if (DTD == 0)
151 IPU_LOG(" Does not decode DT.");
152 else
153 IPU_LOG(" Decodes DT.");
154
155 if (SGN == 0)
156 IPU_LOG(" No bias.");
157 else
158 IPU_LOG(" Bias=128.");
159
160 if (DTE == 1) IPU_LOG(" Dither Enabled.");
161 if (OFM == 0)
162 IPU_LOG(" Output format is RGB32.");
163 else
164 IPU_LOG(" Output format is RGB16.");
165
166 IPU_LOG("");
167 }
168 };
169
170 union tIPU_CMD_BDEC
171 {
172 struct
173 {
174 u32 FB : 6;
175 u32 UN2 :10;
176 u32 QSC : 5;
177 u32 UN1 : 4;
178 u32 DT : 1;
179 u32 DCR : 1;
180 u32 MBI : 1;
181 u32 cmd : 4;
182 };
183 u32 _u32;
184
185 tIPU_CMD_BDEC( u32 val ) { _u32 = val; }
186
187 bool test(u32 flags) const { return !!(_u32 & flags); }
188 void set_flags(u32 flags) { _u32 |= flags; }
189 void clear_flags(u32 flags) { _u32 &= ~flags; }
190 void reset() { _u32 = 0; }
191 void log(int s_bdec)
192 {
193 IPU_LOG("IPU BDEC(macroblock decode) command %x, num: 0x%x", cpuRegs.pc, s_bdec);
194 if (FB) IPU_LOG(" Skip 0x%X bits.", FB);
195
196 if (MBI)
197 IPU_LOG(" Intra MB.");
198 else
199 IPU_LOG(" Non-intra MB.");
200
201 if (DCR)
202 IPU_LOG(" Resets DC prediction value.");
203 else
204 IPU_LOG(" Doesn't reset DC prediction value.");
205
206 if (DT)
207 IPU_LOG(" Use field DCT.");
208 else
209 IPU_LOG(" Use frame DCT.");
210
211 IPU_LOG(" Quantizer step=0x%X", QSC);
212 }
213 };
214
215 union tIPU_CMD_CSC
216 {
217 struct
218 {
219 u32 MBC :11;
220 u32 UN2 :15;
221 u32 DTE : 1;
222 u32 OFM : 1;
223 u32 cmd : 4;
224 };
225 u32 _u32;
226
227 tIPU_CMD_CSC( u32 val ){ _u32 = val; }
228
229 bool test(u32 flags) const { return !!(_u32 & flags); }
230 void set_flags(u32 flags) { _u32 |= flags; }
231 void clear_flags(u32 flags) { _u32 &= ~flags; }
232 void reset() { _u32 = 0; }
233 void log_from_YCbCr()
234 {
235 IPU_LOG("IPU CSC(Colorspace conversion from YCbCr) command (%d).", MBC);
236 if (OFM)
237 IPU_LOG("Output format is RGB16. ");
238 else
239 IPU_LOG("Output format is RGB32. ");
240
241 if (DTE) IPU_LOG("Dithering enabled.");
242 }
243 void log_from_RGB32()
244 {
245 IPU_LOG("IPU PACK (Colorspace conversion from RGB32) command.");
246
247 if (OFM)
248 IPU_LOG("Output format is RGB16. ");
249 else
250 IPU_LOG("Output format is INDX4. ");
251
252 if (DTE) IPU_LOG("Dithering enabled.");
253
254 IPU_LOG("Number of macroblocks to be converted: %d", MBC);
255 }
256 };
257
258 union tIPU_DMA
259 {
260 struct
261 {
262 bool GIFSTALL : 1;
263 bool TIE0 :1;
264 bool TIE1 : 1;
265 bool ACTV1 : 1;
266 bool DOTIE1 : 1;
267 bool FIREINT0 : 1;
268 bool FIREINT1 : 1;
269 bool VIFSTALL : 1;
270 bool SIFSTALL : 1;
271 };
272 u32 _u32;
273
274 tIPU_DMA( u32 val ){ _u32 = val; }
275
276 bool test(u32 flags) const { return !!(_u32 & flags); }
277 void set_flags(u32 flags) { _u32 |= flags; }
278 void clear_flags(u32 flags) { _u32 &= ~flags; }
279 void reset() { _u32 = 0; }
280 wxString desc() const
281 {
282 wxString temp(L"g_nDMATransfer[");
283
284 if (GIFSTALL) temp += L" GIFSTALL ";
285 if (TIE0) temp += L" TIE0 ";
286 if (TIE1) temp += L" TIE1 ";
287 if (ACTV1) temp += L" ACTV1 ";
288 if (DOTIE1) temp += L" DOTIE1 ";
289 if (FIREINT0) temp += L" FIREINT0 ";
290 if (FIREINT1) temp += L" FIREINT1 ";
291 if (VIFSTALL) temp += L" VIFSTALL ";
292 if (SIFSTALL) temp += L" SIFSTALL ";
293
294 temp += L"]";
295 return temp;
296 }
297 };
298
299 enum SCE_IPU
300 {
301 SCE_IPU_BCLR = 0x0
302 , SCE_IPU_IDEC
303 , SCE_IPU_BDEC
304 , SCE_IPU_VDEC
305 , SCE_IPU_FDEC
306 , SCE_IPU_SETIQ
307 , SCE_IPU_SETVQ
308 , SCE_IPU_CSC
309 , SCE_IPU_PACK
310 , SCE_IPU_SETTH
311 };
312
313 struct IPUregisters {
314 tIPU_CMD cmd;
315 u32 dummy0[2];
316 tIPU_CTRL ctrl;
317 u32 dummy1[3];
318 u32 ipubp;
319 u32 dummy2[3];
320 u32 top;
321 u32 topbusy;
322 u32 dummy3[2];
323 };
324
325 #define ipuRegs ((IPUregisters*)(PS2MEM_HW+0x2000))
326
327 struct tIPU_cmd
328 {
329 int index;
330 int pos[2];
331 int current;
332 void clear()
333 {
334 memzero(pos);
335 index = 0;
336 current = 0xffffffff;
337 }
338 wxString desc() const
339 {
340 return wxsFormat(L"Ipu cmd: index = 0x%x, current = 0x%x, pos[0] = 0x%x, pos[1] = 0x%x",
341 index, current, pos[0], pos[1]);
342 }
343 };
344
345 //extern tIPU_cmd ipu_cmd;
346 extern tIPU_BP g_BP;
347 extern int coded_block_pattern;
348 extern int g_nIPU0Data; // or 0x80000000 whenever transferring
349 extern u8* g_pIPU0Pointer;
350
351 // The IPU can only do one task at once and never uses other buffers so these
352 // should be made available to functions in other modules to save registers.
353 extern __aligned16 macroblock_rgb32 rgb32;
354 extern __aligned16 macroblock_8 mb8;
355
356 extern int ipuInit();
357 extern void ipuReset();
358 extern void ipuShutdown();
359 extern int ipuFreeze(gzFile f, int Mode);
360 extern bool ipuCanFreeze();
361
362 extern u32 ipuRead32(u32 mem);
363 extern u64 ipuRead64(u32 mem);
364 extern void ipuWrite32(u32 mem,u32 value);
365 extern void ipuWrite64(u32 mem,u64 value);
366
367 extern void IPUCMD_WRITE(u32 val);
368 extern void ipuSoftReset();
369 extern void IPUProcessInterrupt();
370 extern void ipu0Interrupt();
371 extern void ipu1Interrupt();
372
373 extern void dmaIPU0();
374 extern void dmaIPU1();
375 extern int IPU0dma();
376 extern int IPU1dma();
377
378 extern u16 __fastcall FillInternalBuffer(u32 * pointer, u32 advance, u32 size);
379 extern u8 __fastcall getBits32(u8 *address, u32 advance);
380 extern u8 __fastcall getBits16(u8 *address, u32 advance);
381 extern u8 __fastcall getBits8(u8 *address, u32 advance);
382 extern int __fastcall getBits(u8 *address, u32 size, u32 advance);
383
384
385 #endif

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