/[pcsx2_0.9.7]/trunk/pcsx2/Hw.h
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Contents of /trunk/pcsx2/Hw.h

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Revision 31 - (show annotations) (download)
Tue Sep 7 03:24:11 2010 UTC (9 years, 10 months ago) by william
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committing r3113 initial commit again...
1 /* PCSX2 - PS2 Emulator for PCs
2 * Copyright (C) 2002-2010 PCSX2 Dev Team
3 *
4 * PCSX2 is free software: you can redistribute it and/or modify it under the terms
5 * of the GNU Lesser General Public License as published by the Free Software Found-
6 * ation, either version 3 of the License, or (at your option) any later version.
7 *
8 * PCSX2 is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
9 * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
10 * PURPOSE. See the GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License along with PCSX2.
13 * If not, see <http://www.gnu.org/licenses/>.
14 */
15
16
17 #ifndef __HW_H__
18 #define __HW_H__
19
20 extern void CPU_INT( u32 n, s32 ecycle );
21
22 //////////////////////////////////////////////////////////////////////////
23 // Hardware FIFOs (128 bit access only!)
24 //
25 // VIF0 -- 0x10004000 -- PS2MEM_HW[0x4000]
26 // VIF1 -- 0x10005000 -- PS2MEM_HW[0x5000]
27 // GIF -- 0x10006000 -- PS2MEM_HW[0x6000]
28 // IPUout -- 0x10007000 -- PS2MEM_HW[0x7000]
29 // IPUin -- 0x10007010 -- PS2MEM_HW[0x7010]
30
31 void __fastcall ReadFIFO_page_4(u32 mem, mem128_t *out);
32 void __fastcall ReadFIFO_page_5(u32 mem, mem128_t *out);
33 void __fastcall ReadFIFO_page_6(u32 mem, mem128_t *out);
34 void __fastcall ReadFIFO_page_7(u32 mem, mem128_t *out);
35
36 void __fastcall WriteFIFO_page_4(u32 mem, const mem128_t *value);
37 void __fastcall WriteFIFO_page_5(u32 mem, const mem128_t *value);
38 void __fastcall WriteFIFO_page_6(u32 mem, const mem128_t *value);
39 void __fastcall WriteFIFO_page_7(u32 mem, const mem128_t *value);
40
41 // HW defines
42 enum EERegisterAddresses
43 {
44 RCNT0_COUNT = 0x10000000,
45 RCNT0_MODE = 0x10000010,
46 RCNT0_TARGET = 0x10000020,
47 RCNT0_HOLD = 0x10000030,
48
49 RCNT1_COUNT = 0x10000800,
50 RCNT1_MODE = 0x10000810,
51 RCNT1_TARGET = 0x10000820,
52 RCNT1_HOLD = 0x10000830,
53
54 RCNT2_COUNT = 0x10001000,
55 RCNT2_MODE = 0x10001010,
56 RCNT2_TARGET = 0x10001020,
57
58 RCNT3_COUNT = 0x10001800,
59 RCNT3_MODE = 0x10001810,
60 RCNT3_TARGET = 0x10001820,
61
62 IPU_CMD = 0x10002000,
63 IPU_CTRL = 0x10002010,
64 IPU_BP = 0x10002020,
65 IPU_TOP = 0x10002030,
66
67 GIF_CTRL = 0x10003000,
68 GIF_MODE = 0x10003010,
69 GIF_STAT = 0x10003020,
70 GIF_TAG0 = 0x10003040,
71 GIF_TAG1 = 0x10003050,
72 GIF_TAG2 = 0x10003060,
73 GIF_TAG3 = 0x10003070,
74 GIF_CNT = 0x10003080,
75 GIF_P3CNT = 0x10003090,
76 GIF_P3TAG = 0x100030A0,
77
78 // Vif Memory Locations
79 VIF0_STAT = 0x10003800,
80 VIF0_FBRST = 0x10003810,
81 VIF0_ERR = 0x10003820,
82 VIF0_MARK = 0x10003830,
83 VIF0_CYCLE = 0x10003840,
84 VIF0_MODE = 0x10003850,
85 VIF0_NUM = 0x10003860,
86 VIF0_MASK = 0x10003870,
87 VIF0_CODE = 0x10003880,
88 VIF0_ITOPS = 0x10003890,
89 VIF0_ITOP = 0x100038d0,
90 VIF0_TOP = 0x100038e0,
91 VIF0_R0 = 0x10003900,
92 VIF0_R1 = 0x10003910,
93 VIF0_R2 = 0x10003920,
94 VIF0_R3 = 0x10003930,
95 VIF0_C0 = 0x10003940,
96 VIF0_C1 = 0x10003950,
97 VIF0_C2 = 0x10003960,
98 VIF0_C3 = 0x10003970,
99
100 VIF1_STAT = 0x10003c00,
101 VIF1_FBRST = 0x10003c10,
102 VIF1_ERR = 0x10003c20,
103 VIF1_MARK = 0x10003c30,
104 VIF1_CYCLE = 0x10003c40,
105 VIF1_MODE = 0x10003c50,
106 VIF1_NUM = 0x10003c60,
107 VIF1_MASK = 0x10003c70,
108 VIF1_CODE = 0x10003c80,
109 VIF1_ITOPS = 0x10003c90,
110 VIF1_BASE = 0x10003ca0,
111 VIF1_OFST = 0x10003cb0,
112 VIF1_TOPS = 0x10003cc0,
113 VIF1_ITOP = 0x10003cd0,
114 VIF1_TOP = 0x10003ce0,
115 VIF1_R0 = 0x10003d00,
116 VIF1_R1 = 0x10003d10,
117 VIF1_R2 = 0x10003d20,
118 VIF1_R3 = 0x10003d30,
119 VIF1_C0 = 0x10003d40,
120 VIF1_C1 = 0x10003d50,
121 VIF1_C2 = 0x10003d60,
122 VIF1_C3 = 0x10003d70,
123
124 VIF0_FIFO = 0x10004000,
125 VIF1_FIFO = 0x10005000,
126 GIF_FIFO = 0x10006000,
127
128 IPUout_FIFO = 0x10007000,
129 IPUin_FIFO = 0x10007010,
130
131 //VIF0
132 D0_CHCR = 0x10008000,
133 D0_MADR = 0x10008010,
134 D0_QWC = 0x10008020,
135
136 //VIF1
137 D1_CHCR = 0x10009000,
138 D1_MADR = 0x10009010,
139 D1_QWC = 0x10009020,
140 D1_TADR = 0x10009030,
141 D1_ASR0 = 0x10009040,
142 D1_ASR1 = 0x10009050,
143 D1_SADR = 0x10009080,
144
145 //GS
146 D2_CHCR = 0x1000A000,
147 D2_MADR = 0x1000A010,
148 D2_QWC = 0x1000A020,
149 D2_TADR = 0x1000A030,
150 D2_ASR0 = 0x1000A040,
151 D2_ASR1 = 0x1000A050,
152 D2_SADR = 0x1000A080,
153
154 //fromIPU
155 D3_CHCR = 0x1000B000,
156 D3_MADR = 0x1000B010,
157 D3_QWC = 0x1000B020,
158 D3_TADR = 0x1000B030,
159 D3_SADR = 0x1000B080,
160
161 //toIPU
162 D4_CHCR = 0x1000B400,
163 D4_MADR = 0x1000B410,
164 D4_QWC = 0x1000B420,
165 D4_TADR = 0x1000B430,
166 D4_SADR = 0x1000B480,
167
168 //SIF0
169 D5_CHCR = 0x1000C000,
170 D5_MADR = 0x1000C010,
171 D5_QWC = 0x1000C020,
172
173 //SIF1
174 D6_CHCR = 0x1000C400,
175 D6_MADR = 0x1000C410,
176 D6_QWC = 0x1000C420,
177 D6_TADR = 0x1000C430,
178
179 //SIF2
180 D7_CHCR = 0x1000C800,
181 D7_MADR = 0x1000C810,
182 D7_QWC = 0x1000C820,
183
184 //fromSPR
185 D8_CHCR = 0x1000D000,
186 D8_MADR = 0x1000D010,
187 D8_QWC = 0x1000D020,
188 D8_SADR = 0x1000D080,
189 D9_CHCR = 0x1000D400,
190
191 DMAC_CTRL = 0x1000E000,
192 DMAC_STAT = 0x1000E010,
193 DMAC_PCR = 0x1000E020,
194 DMAC_SQWC = 0x1000E030,
195 DMAC_RBSR = 0x1000E040,
196 DMAC_RBOR = 0x1000E050,
197 DMAC_STADR = 0x1000E060,
198
199 INTC_STAT = 0x1000F000,
200 INTC_MASK = 0x1000F010,
201
202 SIO_LCR = 0x1000F100,
203 SIO_LSR = 0x1000F110,
204 SIO_IER = 0x1000F120,
205 SIO_ISR = 0x1000F130,//
206 SIO_FCR = 0x1000F140,
207 SIO_BGR = 0x1000F150,
208 SIO_TXFIFO = 0x1000F180,
209 SIO_RXFIFO = 0x1000F1C0,
210
211 SBUS_F200 = 0x1000F200, //MSCOM
212 SBUS_F210 = 0x1000F210, //SMCOM
213 SBUS_F220 = 0x1000F220, //MSFLG
214 SBUS_F230 = 0x1000F230, //SMFLG
215 SBUS_F240 = 0x1000F240,
216 SBUS_F250 = 0x1000F250,
217 SBUS_F260 = 0x1000F260,
218
219 MCH_RICM = 0x1000F430,
220 MCH_DRD = 0x1000F440,
221
222 DMAC_ENABLER = 0x1000F520,
223 DMAC_ENABLEW = 0x1000F590
224 };
225
226 enum GSRegisterAddresses
227 {
228 GS_PMODE = 0x12000000,
229 GS_SMODE1 = 0x12000010,
230 GS_SMODE2 = 0x12000020,
231 GS_SRFSH = 0x12000030,
232 GS_SYNCH1 = 0x12000040,
233 GS_SYNCH2 = 0x12000050,
234 GS_SYNCV = 0x12000060,
235 GS_DISPFB1 = 0x12000070,
236 GS_DISPLAY1 = 0x12000080,
237 GS_DISPFB2 = 0x12000090,
238 GS_DISPLAY2 = 0x120000A0,
239 GS_EXTBUF = 0x120000B0,
240 GS_EXTDATA = 0x120000C0,
241 GS_EXTWRITE = 0x120000D0,
242 GS_BGCOLOR = 0x120000E0,
243 GS_CSR = 0x12001000,
244 GS_IMR = 0x12001010,
245 GS_BUSDIR = 0x12001040,
246 GS_SIGLBLID = 0x12001080
247 };
248
249 // bleh, I'm graindead -- air
250 union tGS_SMODE2
251 {
252 struct
253 {
254 u32 INT:1;
255 u32 FFMD:1;
256 u32 DPMS:2;
257 u32 _PAD2:28;
258 u32 _PAD3:32;
259 };
260
261 u64 _u64;
262
263 bool IsInterlaced() const { return INT; }
264 };
265
266 void hwReset();
267
268 // hw read functions
269 extern mem8_t hwRead8 (u32 mem);
270 extern mem16_t hwRead16(u32 mem);
271
272 extern mem32_t __fastcall hwRead32_page_00(u32 mem);
273 extern mem32_t __fastcall hwRead32_page_01(u32 mem);
274 extern mem32_t __fastcall hwRead32_page_02(u32 mem);
275 extern mem32_t __fastcall hwRead32_page_0F(u32 mem);
276 extern mem32_t __fastcall hwRead32_page_0F_INTC_HACK(u32 mem);
277 extern mem32_t __fastcall hwRead32_generic(u32 mem);
278
279 extern void __fastcall hwRead64_page_00(u32 mem, mem64_t* result );
280 extern void __fastcall hwRead64_page_01(u32 mem, mem64_t* result );
281 extern void __fastcall hwRead64_page_02(u32 mem, mem64_t* result );
282 extern void __fastcall hwRead64_generic_INTC_HACK(u32 mem, mem64_t *out);
283 extern void __fastcall hwRead64_generic(u32 mem, mem64_t* result );
284
285 extern void __fastcall hwRead128_page_00(u32 mem, mem128_t* result );
286 extern void __fastcall hwRead128_page_01(u32 mem, mem128_t* result );
287 extern void __fastcall hwRead128_page_02(u32 mem, mem128_t* result );
288 extern void __fastcall hwRead128_generic(u32 mem, mem128_t *out);
289
290 // hw write functions
291 extern void hwWrite8 (u32 mem, u8 value);
292 extern void hwWrite16(u32 mem, u16 value);
293
294 extern void __fastcall hwWrite32_page_00( u32 mem, mem32_t value );
295 extern void __fastcall hwWrite32_page_01( u32 mem, mem32_t value );
296 extern void __fastcall hwWrite32_page_02( u32 mem, mem32_t value );
297 extern void __fastcall hwWrite32_page_03( u32 mem, mem32_t value );
298 extern void __fastcall hwWrite32_page_0B( u32 mem, mem32_t value );
299 extern void __fastcall hwWrite32_page_0E( u32 mem, mem32_t value );
300 extern void __fastcall hwWrite32_page_0F( u32 mem, mem32_t value );
301 extern void __fastcall hwWrite32_generic( u32 mem, mem32_t value );
302
303 extern void __fastcall hwWrite64_page_00( u32 mem, const mem64_t* srcval );
304 extern void __fastcall hwWrite64_page_01( u32 mem, const mem64_t* srcval );
305 extern void __fastcall hwWrite64_page_02( u32 mem, const mem64_t* srcval );
306 extern void __fastcall hwWrite64_page_03( u32 mem, const mem64_t* srcval );
307 extern void __fastcall hwWrite64_page_0E( u32 mem, const mem64_t* srcval );
308 extern void __fastcall hwWrite64_generic( u32 mem, const mem64_t* srcval );
309
310 extern void __fastcall hwWrite128_generic(u32 mem, const mem128_t *srcval);
311
312 bool hwMFIFOWrite(u32 addr, u8 *data, u32 size);
313
314 extern const int rdram_devices;
315 extern int rdram_sdevid;
316
317 #endif /* __HW_H__ */

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