/[pcsx2_0.9.7]/trunk/pcsx2/Hw.h
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Annotation of /trunk/pcsx2/Hw.h

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Tue Sep 7 11:08:22 2010 UTC (9 years, 10 months ago) by william
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Auto Commited Import of: pcsx2-0.9.7-r3738-debug in ./trunk
1 william 31 /* PCSX2 - PS2 Emulator for PCs
2     * Copyright (C) 2002-2010 PCSX2 Dev Team
3     *
4     * PCSX2 is free software: you can redistribute it and/or modify it under the terms
5     * of the GNU Lesser General Public License as published by the Free Software Found-
6     * ation, either version 3 of the License, or (at your option) any later version.
7     *
8     * PCSX2 is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
9     * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
10     * PURPOSE. See the GNU General Public License for more details.
11     *
12     * You should have received a copy of the GNU General Public License along with PCSX2.
13     * If not, see <http://www.gnu.org/licenses/>.
14     */
15    
16 william 62 #pragma once
17 william 31
18 william 62 namespace EEMemoryMap
19     {
20     static const uint RCNT0_Start = 0x10000000;
21     static const uint RCNT0_End = 0x10000800;
22     static const uint RCNT1_Start = 0x10000800;
23     static const uint RCNT1_End = 0x10001000;
24     static const uint RCNT2_Start = 0x10001000;
25     static const uint RCNT2_End = 0x10001800;
26     static const uint RCNT3_Start = 0x10001800;
27     static const uint RCNT3_End = 0x10002000;
28 william 31
29 william 62 static const uint IPU_Start = 0x10002000;
30     static const uint IPU_End = 0x10003000;
31 william 31
32 william 62 static const uint GIF_Start = 0x10003000;
33     static const uint GIF_End = 0x10003800;
34 william 31
35 william 62 static const uint VIF0_Start = 0x10003800;
36     static const uint VIF0_End = 0x10003C00;
37     static const uint VIF1_Start = 0x10003C00;
38     static const uint VIF1_End = 0x10004000;
39 william 31
40 william 62 static const uint VIF0_FIFO_Start = 0x10004000;
41     static const uint VIF0_FIFO_End = 0x10005000;
42     static const uint VIF1_FIFO_Start = 0x10005000;
43     static const uint VIF1_FIFO_End = 0x10006000;
44     static const uint GIF_FIFO_Start = 0x10006000;
45     static const uint GIF_FIFO_End = 0x10007000;
46     static const uint IPU_FIFO_Start = 0x10007000;
47     static const uint IPU_FIFO_End = 0x10008000;
48 william 31
49 william 62 static const uint VIF0dma_Start = 0x10008000;
50     static const uint VIF0dma_End = 0x10009000;
51     static const uint VIF1dma_Start = 0x10009000;
52     static const uint VIF1dma_End = 0x1000A000;
53    
54     static const uint GIFdma_Start = 0x1000A000;
55     static const uint GIFdma_End = 0x1000B000;
56    
57     static const uint fromIPU_Start = 0x1000B000;
58     static const uint fromIPU_End = 0x1000B400;
59     static const uint toIPU_Start = 0x1000B400;
60     static const uint toIPU_End = 0x1000C000;
61    
62     static const uint SIF0dma_Start = 0x1000C000;
63     static const uint SIF0dma_End = 0x1000C400;
64     static const uint SIF1dma_Start = 0x1000C400;
65     static const uint SIF1dma_End = 0x1000C800;
66     static const uint SIF2dma_Start = 0x1000C800;
67     static const uint SIF2dma_End = 0x1000D000;
68    
69     static const uint fromSPR_Start = 0x1000D000;
70     static const uint fromSPR_End = 0x1000D400;
71     static const uint toSPR_Start = 0x1000D400;
72     static const uint toSPR_End = 0x1000E000;
73    
74     static const uint DMAC_Start = 0x1000E000;
75     static const uint DMAC_End = 0x1000F000;
76    
77     static const uint INTC_Start = 0x1000F000;
78     static const uint INTC_End = 0x1000F100;
79    
80     static const uint SIO_Start = 0x1000F100;
81     static const uint SIO_End = 0x1000F200;
82     static const uint SBUS_Start = 0x1000F200;
83     static const uint SBUS_End = 0x1000F400;
84    
85     // MCH area -- Really not sure what this area is. Information is lacking.
86     static const uint MCH_Start = 0x1000F400;
87     static const uint MCH_End = 0x1000F500;
88    
89     // Extended master control register area for DMAC.
90     static const uint DMACext_Start = 0x1000F500;
91     static const uint DMACext_End = 0x1000F600;
92    
93     };
94    
95 william 31 // HW defines
96     enum EERegisterAddresses
97     {
98     RCNT0_COUNT = 0x10000000,
99     RCNT0_MODE = 0x10000010,
100     RCNT0_TARGET = 0x10000020,
101     RCNT0_HOLD = 0x10000030,
102    
103     RCNT1_COUNT = 0x10000800,
104     RCNT1_MODE = 0x10000810,
105     RCNT1_TARGET = 0x10000820,
106     RCNT1_HOLD = 0x10000830,
107    
108     RCNT2_COUNT = 0x10001000,
109     RCNT2_MODE = 0x10001010,
110     RCNT2_TARGET = 0x10001020,
111    
112     RCNT3_COUNT = 0x10001800,
113     RCNT3_MODE = 0x10001810,
114     RCNT3_TARGET = 0x10001820,
115    
116     IPU_CMD = 0x10002000,
117     IPU_CTRL = 0x10002010,
118     IPU_BP = 0x10002020,
119     IPU_TOP = 0x10002030,
120    
121     GIF_CTRL = 0x10003000,
122     GIF_MODE = 0x10003010,
123     GIF_STAT = 0x10003020,
124     GIF_TAG0 = 0x10003040,
125     GIF_TAG1 = 0x10003050,
126     GIF_TAG2 = 0x10003060,
127     GIF_TAG3 = 0x10003070,
128     GIF_CNT = 0x10003080,
129     GIF_P3CNT = 0x10003090,
130     GIF_P3TAG = 0x100030A0,
131    
132     // Vif Memory Locations
133     VIF0_STAT = 0x10003800,
134     VIF0_FBRST = 0x10003810,
135     VIF0_ERR = 0x10003820,
136     VIF0_MARK = 0x10003830,
137     VIF0_CYCLE = 0x10003840,
138     VIF0_MODE = 0x10003850,
139     VIF0_NUM = 0x10003860,
140     VIF0_MASK = 0x10003870,
141     VIF0_CODE = 0x10003880,
142     VIF0_ITOPS = 0x10003890,
143     VIF0_ITOP = 0x100038d0,
144     VIF0_TOP = 0x100038e0,
145 william 62 VIF0_ROW0 = 0x10003900,
146     VIF0_ROW1 = 0x10003910,
147     VIF0_ROW2 = 0x10003920,
148     VIF0_ROW3 = 0x10003930,
149     VIF0_COL0 = 0x10003940,
150     VIF0_COL1 = 0x10003950,
151     VIF0_COL2 = 0x10003960,
152     VIF0_COL3 = 0x10003970,
153 william 31
154     VIF1_STAT = 0x10003c00,
155     VIF1_FBRST = 0x10003c10,
156     VIF1_ERR = 0x10003c20,
157     VIF1_MARK = 0x10003c30,
158     VIF1_CYCLE = 0x10003c40,
159     VIF1_MODE = 0x10003c50,
160     VIF1_NUM = 0x10003c60,
161     VIF1_MASK = 0x10003c70,
162     VIF1_CODE = 0x10003c80,
163     VIF1_ITOPS = 0x10003c90,
164     VIF1_BASE = 0x10003ca0,
165     VIF1_OFST = 0x10003cb0,
166     VIF1_TOPS = 0x10003cc0,
167     VIF1_ITOP = 0x10003cd0,
168     VIF1_TOP = 0x10003ce0,
169 william 62 VIF1_ROW0 = 0x10003d00,
170     VIF1_ROW1 = 0x10003d10,
171     VIF1_ROW2 = 0x10003d20,
172     VIF1_ROW3 = 0x10003d30,
173     VIF1_COL0 = 0x10003d40,
174     VIF1_COL1 = 0x10003d50,
175     VIF1_COL2 = 0x10003d60,
176     VIF1_COL3 = 0x10003d70,
177 william 31
178     VIF0_FIFO = 0x10004000,
179     VIF1_FIFO = 0x10005000,
180     GIF_FIFO = 0x10006000,
181    
182     IPUout_FIFO = 0x10007000,
183     IPUin_FIFO = 0x10007010,
184    
185     //VIF0
186     D0_CHCR = 0x10008000,
187     D0_MADR = 0x10008010,
188     D0_QWC = 0x10008020,
189 william 62 D0_TADR = 0x10008030,
190     D0_ASR0 = 0x10008040,
191     D0_ASR1 = 0x10008050,
192 william 31
193 william 62 VIF0_CHCR = 0x10008000,
194     VIF0_MADR = 0x10008010,
195     VIF0_QWC = 0x10008020,
196     VIF0_TADR = 0x10008030,
197     VIF0_ASR0 = 0x10008040,
198     VIF0_ASR1 = 0x10008050,
199    
200 william 31 //VIF1
201     D1_CHCR = 0x10009000,
202     D1_MADR = 0x10009010,
203     D1_QWC = 0x10009020,
204     D1_TADR = 0x10009030,
205     D1_ASR0 = 0x10009040,
206     D1_ASR1 = 0x10009050,
207    
208 william 62 VIF1_CHCR = 0x10009000,
209     VIF1_MADR = 0x10009010,
210     VIF1_QWC = 0x10009020,
211     VIF1_TADR = 0x10009030,
212     VIF1_ASR0 = 0x10009040,
213     VIF1_ASR1 = 0x10009050,
214    
215 william 31 //GS
216     D2_CHCR = 0x1000A000,
217     D2_MADR = 0x1000A010,
218     D2_QWC = 0x1000A020,
219     D2_TADR = 0x1000A030,
220     D2_ASR0 = 0x1000A040,
221     D2_ASR1 = 0x1000A050,
222    
223 william 62 GIF_CHCR = 0x1000A000,
224     GIF_MADR = 0x1000A010,
225     GIF_QWC = 0x1000A020,
226     GIF_TADR = 0x1000A030,
227     GIF_ASR0 = 0x1000A040,
228     GIF_ASR1 = 0x1000A050,
229    
230 william 31 //fromIPU
231     D3_CHCR = 0x1000B000,
232     D3_MADR = 0x1000B010,
233     D3_QWC = 0x1000B020,
234     D3_TADR = 0x1000B030,
235    
236 william 62 fromIPU_CHCR = 0x1000B000,
237     fromIPU_MADR = 0x1000B010,
238     fromIPU_QWC = 0x1000B020,
239     fromIPU_TADR = 0x1000B030,
240    
241 william 31 //toIPU
242     D4_CHCR = 0x1000B400,
243     D4_MADR = 0x1000B410,
244     D4_QWC = 0x1000B420,
245     D4_TADR = 0x1000B430,
246    
247 william 62 toIPU_CHCR = 0x1000B400,
248     toIPU_MADR = 0x1000B410,
249     toIPU_QWC = 0x1000B420,
250     toIPU_TADR = 0x1000B430,
251    
252 william 31 //SIF0
253     D5_CHCR = 0x1000C000,
254     D5_MADR = 0x1000C010,
255     D5_QWC = 0x1000C020,
256    
257 william 62 SIF0_CHCR = 0x1000C000,
258     SIF0_MADR = 0x1000C010,
259     SIF0_QWC = 0x1000C020,
260    
261 william 31 //SIF1
262     D6_CHCR = 0x1000C400,
263     D6_MADR = 0x1000C410,
264     D6_QWC = 0x1000C420,
265     D6_TADR = 0x1000C430,
266    
267 william 62 SIF1_CHCR = 0x1000C400,
268     SIF1_MADR = 0x1000C410,
269     SIF1_QWC = 0x1000C420,
270     SIF1_TADR = 0x1000C430,
271    
272 william 31 //SIF2
273     D7_CHCR = 0x1000C800,
274     D7_MADR = 0x1000C810,
275     D7_QWC = 0x1000C820,
276    
277 william 62 SIF2_CHCR = 0x1000C800,
278     SIF2_MADR = 0x1000C810,
279     SIF2_QWC = 0x1000C820,
280    
281 william 31 //fromSPR
282     D8_CHCR = 0x1000D000,
283     D8_MADR = 0x1000D010,
284     D8_QWC = 0x1000D020,
285    
286 william 62 fromSPR_CHCR = 0x1000D000,
287     fromSPR_MADR = 0x1000D010,
288     fromSPR_QWC = 0x1000D020,
289    
290     //toSPR
291     D9_CHCR = 0x1000D400,
292     D9_MADR = 0x1000D010,
293     D9_QWC = 0x1000D020,
294    
295     toSPR_CHCR = 0x1000D400,
296     toSPR_MADR = 0x1000D410,
297     toSPR_QWC = 0x1000D420,
298    
299 william 31 DMAC_CTRL = 0x1000E000,
300     DMAC_STAT = 0x1000E010,
301     DMAC_PCR = 0x1000E020,
302     DMAC_SQWC = 0x1000E030,
303     DMAC_RBSR = 0x1000E040,
304     DMAC_RBOR = 0x1000E050,
305     DMAC_STADR = 0x1000E060,
306    
307     INTC_STAT = 0x1000F000,
308     INTC_MASK = 0x1000F010,
309    
310     SIO_LCR = 0x1000F100,
311     SIO_LSR = 0x1000F110,
312     SIO_IER = 0x1000F120,
313     SIO_ISR = 0x1000F130,//
314     SIO_FCR = 0x1000F140,
315     SIO_BGR = 0x1000F150,
316     SIO_TXFIFO = 0x1000F180,
317     SIO_RXFIFO = 0x1000F1C0,
318    
319     SBUS_F200 = 0x1000F200, //MSCOM
320     SBUS_F210 = 0x1000F210, //SMCOM
321     SBUS_F220 = 0x1000F220, //MSFLG
322     SBUS_F230 = 0x1000F230, //SMFLG
323     SBUS_F240 = 0x1000F240,
324     SBUS_F250 = 0x1000F250,
325     SBUS_F260 = 0x1000F260,
326    
327     MCH_RICM = 0x1000F430,
328     MCH_DRD = 0x1000F440,
329    
330     DMAC_ENABLER = 0x1000F520,
331     DMAC_ENABLEW = 0x1000F590
332     };
333    
334     enum GSRegisterAddresses
335     {
336     GS_PMODE = 0x12000000,
337     GS_SMODE1 = 0x12000010,
338     GS_SMODE2 = 0x12000020,
339     GS_SRFSH = 0x12000030,
340     GS_SYNCH1 = 0x12000040,
341     GS_SYNCH2 = 0x12000050,
342     GS_SYNCV = 0x12000060,
343     GS_DISPFB1 = 0x12000070,
344     GS_DISPLAY1 = 0x12000080,
345     GS_DISPFB2 = 0x12000090,
346     GS_DISPLAY2 = 0x120000A0,
347     GS_EXTBUF = 0x120000B0,
348     GS_EXTDATA = 0x120000C0,
349     GS_EXTWRITE = 0x120000D0,
350     GS_BGCOLOR = 0x120000E0,
351     GS_CSR = 0x12001000,
352     GS_IMR = 0x12001010,
353     GS_BUSDIR = 0x12001040,
354     GS_SIGLBLID = 0x12001080
355     };
356    
357     // bleh, I'm graindead -- air
358     union tGS_SMODE2
359     {
360     struct
361     {
362     u32 INT:1;
363     u32 FFMD:1;
364     u32 DPMS:2;
365     u32 _PAD2:28;
366     u32 _PAD3:32;
367     };
368    
369     u64 _u64;
370    
371     bool IsInterlaced() const { return INT; }
372     };
373    
374 william 62 extern void hwReset();
375 william 31
376     extern const int rdram_devices;
377     extern int rdram_sdevid;

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