/[pcsx2_0.9.7]/trunk/pcsx2/DebugTools/DisVUmicro.h
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Contents of /trunk/pcsx2/DebugTools/DisVUmicro.h

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Revision 31 - (show annotations) (download)
Tue Sep 7 03:24:11 2010 UTC (9 years, 9 months ago) by william
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committing r3113 initial commit again...
1 /* PCSX2 - PS2 Emulator for PCs
2 * Copyright (C) 2002-2010 PCSX2 Dev Team
3 *
4 * PCSX2 is free software: you can redistribute it and/or modify it under the terms
5 * of the GNU Lesser General Public License as published by the Free Software Found-
6 * ation, either version 3 of the License, or (at your option) any later version.
7 *
8 * PCSX2 is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
9 * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
10 * PURPOSE. See the GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License along with PCSX2.
13 * If not, see <http://www.gnu.org/licenses/>.
14 */
15
16
17 #define _disVUTables(VU) \
18 \
19 /****************/ \
20 /* LOWER TABLES */ \
21 /****************/ \
22 \
23 TdisR5900F dis##VU##LowerOP_T3_00_OPCODE[32] = { \
24 disNULL , disNULL , disNULL , disNULL , \
25 disNULL , disNULL , disNULL , disNULL , \
26 disNULL , disNULL , disNULL , disNULL , \
27 dis##VU##MI_MOVE , dis##VU##MI_LQI , dis##VU##MI_DIV , dis##VU##MI_MTIR, \
28 dis##VU##MI_RNEXT , disNULL , disNULL , disNULL , /* 0x10 */ \
29 disNULL , disNULL , disNULL , disNULL , \
30 disNULL , dis##VU##MI_MFP , dis##VU##MI_XTOP , dis##VU##MI_XGKICK, \
31 dis##VU##MI_ESADD , dis##VU##MI_EATANxy, dis##VU##MI_ESQRT, dis##VU##MI_ESIN, \
32 }; \
33 \
34 TdisR5900F dis##VU##LowerOP_T3_01_OPCODE[32] = { \
35 disNULL , disNULL , disNULL , disNULL , \
36 disNULL , disNULL , disNULL , disNULL , \
37 disNULL , disNULL , disNULL , disNULL , \
38 dis##VU##MI_MR32 , dis##VU##MI_SQI , dis##VU##MI_SQRT , dis##VU##MI_MFIR, \
39 dis##VU##MI_RGET , disNULL , disNULL , disNULL , /* 0x10 */ \
40 disNULL , disNULL , disNULL , disNULL , \
41 disNULL , disNULL , dis##VU##MI_XITOP, disNULL , \
42 dis##VU##MI_ERSADD, dis##VU##MI_EATANxz, dis##VU##MI_ERSQRT, dis##VU##MI_EATAN, \
43 }; \
44 \
45 TdisR5900F dis##VU##LowerOP_T3_10_OPCODE[32] = { \
46 disNULL , disNULL , disNULL , disNULL , \
47 disNULL , disNULL , disNULL , disNULL , \
48 disNULL , disNULL , disNULL , disNULL , \
49 disNULL , dis##VU##MI_LQD , dis##VU##MI_RSQRT, dis##VU##MI_ILWR, \
50 dis##VU##MI_RINIT , disNULL , disNULL , disNULL , /* 0x10 */ \
51 disNULL , disNULL , disNULL , disNULL , \
52 disNULL , disNULL , disNULL , disNULL , \
53 dis##VU##MI_ELENG , dis##VU##MI_ESUM , dis##VU##MI_ERCPR, dis##VU##MI_EEXP, \
54 }; \
55 \
56 TdisR5900F dis##VU##LowerOP_T3_11_OPCODE[32] = { \
57 disNULL , disNULL , disNULL , disNULL , \
58 disNULL , disNULL , disNULL , disNULL , \
59 disNULL , disNULL , disNULL , disNULL , \
60 disNULL , dis##VU##MI_SQD , dis##VU##MI_WAITQ, dis##VU##MI_ISWR, \
61 dis##VU##MI_RXOR , disNULL , disNULL , disNULL , /* 0x10 */ \
62 disNULL , disNULL , disNULL , disNULL , \
63 disNULL , disNULL , disNULL , disNULL , \
64 dis##VU##MI_ERLENG, disNULL , dis##VU##MI_WAITP, disNULL , \
65 }; \
66 \
67 MakeDisF(dis##VU##LowerOP_T3_00, dis##VU##LowerOP_T3_00_OPCODE[_Fd_] DisFInterfaceN) \
68 MakeDisF(dis##VU##LowerOP_T3_01, dis##VU##LowerOP_T3_01_OPCODE[_Fd_] DisFInterfaceN) \
69 MakeDisF(dis##VU##LowerOP_T3_10, dis##VU##LowerOP_T3_10_OPCODE[_Fd_] DisFInterfaceN) \
70 MakeDisF(dis##VU##LowerOP_T3_11, dis##VU##LowerOP_T3_11_OPCODE[_Fd_] DisFInterfaceN) \
71 \
72 TdisR5900F dis##VU##LowerOP_OPCODE[64] = { \
73 disNULL , disNULL , disNULL , disNULL , \
74 disNULL , disNULL , disNULL , disNULL , \
75 disNULL , disNULL , disNULL , disNULL , \
76 disNULL , disNULL , disNULL , disNULL , \
77 disNULL , disNULL , disNULL , disNULL , /* 0x10 */ \
78 disNULL , disNULL , disNULL , disNULL , \
79 disNULL , disNULL , disNULL , disNULL , \
80 disNULL , disNULL , disNULL , disNULL , \
81 disNULL , disNULL , disNULL , disNULL , /* 0x20 */ \
82 disNULL , disNULL , disNULL , disNULL , \
83 disNULL , disNULL , disNULL , disNULL , \
84 disNULL , disNULL , disNULL , disNULL , \
85 dis##VU##MI_IADD , dis##VU##MI_ISUB , dis##VU##MI_IADDI, disNULL , /* 0x30 */ \
86 dis##VU##MI_IAND , dis##VU##MI_IOR , disNULL , disNULL , \
87 disNULL , disNULL , disNULL , disNULL , \
88 dis##VU##LowerOP_T3_00, dis##VU##LowerOP_T3_01, dis##VU##LowerOP_T3_10, dis##VU##LowerOP_T3_11, \
89 }; \
90 \
91 MakeDisF(dis##VU##LowerOP, dis##VU##LowerOP_OPCODE[code & 0x3f] DisFInterfaceN) \
92 \
93 TdisR5900F dis##VU##MicroL[] = { \
94 dis##VU##MI_LQ , dis##VU##MI_SQ , disNULL , disNULL, \
95 dis##VU##MI_ILW , dis##VU##MI_ISW , disNULL , disNULL, \
96 dis##VU##MI_IADDIU, dis##VU##MI_ISUBIU, disNULL , disNULL, \
97 disNULL , disNULL , disNULL , disNULL, \
98 dis##VU##MI_FCEQ , dis##VU##MI_FCSET , dis##VU##MI_FCAND, dis##VU##MI_FCOR, /* 0x10 */ \
99 dis##VU##MI_FSEQ , dis##VU##MI_FSSET , dis##VU##MI_FSAND, dis##VU##MI_FSOR, \
100 dis##VU##MI_FMEQ , disNULL , dis##VU##MI_FMAND, dis##VU##MI_FMOR, \
101 dis##VU##MI_FCGET , disNULL , disNULL , disNULL, \
102 dis##VU##MI_B , dis##VU##MI_BAL , disNULL , disNULL, /* 0x20 */ \
103 dis##VU##MI_JR , dis##VU##MI_JALR , disNULL , disNULL, \
104 dis##VU##MI_IBEQ , dis##VU##MI_IBNE , disNULL , disNULL, \
105 dis##VU##MI_IBLTZ , dis##VU##MI_IBGTZ , dis##VU##MI_IBLEZ, dis##VU##MI_IBGEZ, \
106 disNULL , disNULL , disNULL , disNULL, /* 0x30 */ \
107 disNULL , disNULL , disNULL , disNULL, \
108 disNULL , disNULL , disNULL , disNULL, \
109 disNULL , disNULL , disNULL , disNULL, \
110 dis##VU##LowerOP , disNULL , disNULL , disNULL, /* 0x40*/ \
111 disNULL , disNULL , disNULL , disNULL, \
112 disNULL , disNULL , disNULL , disNULL, \
113 disNULL , disNULL , disNULL , disNULL, \
114 disNULL , disNULL , disNULL , disNULL, /* 0x50 */ \
115 disNULL , disNULL , disNULL , disNULL, \
116 disNULL , disNULL , disNULL , disNULL, \
117 disNULL , disNULL , disNULL , disNULL, \
118 disNULL , disNULL , disNULL , disNULL, /* 0x60 */ \
119 disNULL , disNULL , disNULL , disNULL, \
120 disNULL , disNULL , disNULL , disNULL, \
121 disNULL , disNULL , disNULL , disNULL, \
122 disNULL , disNULL , disNULL , disNULL, /* 0x70 */ \
123 disNULL , disNULL , disNULL , disNULL, \
124 disNULL , disNULL , disNULL , disNULL, \
125 disNULL , disNULL , disNULL , disNULL, \
126 }; \
127 \
128 \
129 MakeDisF(dis##VU##MicroLF, dis##VU##MicroL[code >> 25] DisFInterfaceN) \
130 \
131 \
132 /****************/ \
133 /* UPPER TABLES */ \
134 /****************/ \
135 \
136 TdisR5900F dis##VU##_UPPER_FD_00_TABLE[32] = { \
137 dis##VU##MI_ADDAx, dis##VU##MI_SUBx , dis##VU##MI_MADDAx, dis##VU##MI_MSUBAx, \
138 dis##VU##MI_ITOF0, dis##VU##MI_FTOI0, dis##VU##MI_MULAx , dis##VU##MI_MULAq , \
139 dis##VU##MI_ADDAq, dis##VU##MI_SUBAq, dis##VU##MI_ADDA , dis##VU##MI_SUBA , \
140 disNULL , disNULL , disNULL , disNULL , \
141 disNULL , disNULL , disNULL , disNULL , \
142 disNULL , disNULL , disNULL , disNULL , \
143 disNULL , disNULL , disNULL , disNULL , \
144 disNULL , disNULL , disNULL , disNULL , \
145 }; \
146 \
147 TdisR5900F dis##VU##_UPPER_FD_01_TABLE[32] = { \
148 dis##VU##MI_ADDAy , dis##VU##MI_SUBy , dis##VU##MI_MADDAy, dis##VU##MI_MSUBAy, \
149 dis##VU##MI_ITOF4 , dis##VU##MI_FTOI4 , dis##VU##MI_MULAy , dis##VU##MI_ABS , \
150 dis##VU##MI_MADDAq, dis##VU##MI_MSUBAq, dis##VU##MI_MADDA , dis##VU##MI_MSUBA , \
151 disNULL , disNULL , disNULL , disNULL , \
152 disNULL , disNULL , disNULL , disNULL , \
153 disNULL , disNULL , disNULL , disNULL , \
154 disNULL , disNULL , disNULL , disNULL , \
155 disNULL , disNULL , disNULL , disNULL , \
156 }; \
157 \
158 TdisR5900F dis##VU##_UPPER_FD_10_TABLE[32] = { \
159 dis##VU##MI_ADDAz , dis##VU##MI_SUBz , dis##VU##MI_MADDAz, dis##VU##MI_MSUBAz, \
160 dis##VU##MI_ITOF12, dis##VU##MI_FTOI12, dis##VU##MI_MULAz , dis##VU##MI_MULAi , \
161 dis##VU##MI_ADDAi, dis##VU##MI_SUBAi , dis##VU##MI_MULA , dis##VU##MI_OPMULA, \
162 disNULL , disNULL , disNULL , disNULL , \
163 disNULL , disNULL , disNULL , disNULL , \
164 disNULL , disNULL , disNULL , disNULL , \
165 disNULL , disNULL , disNULL , disNULL , \
166 disNULL , disNULL , disNULL , disNULL , \
167 }; \
168 \
169 TdisR5900F dis##VU##_UPPER_FD_11_TABLE[32] = { \
170 dis##VU##MI_ADDAw , dis##VU##MI_SUBw , dis##VU##MI_MADDAw, dis##VU##MI_MSUBAw, \
171 dis##VU##MI_ITOF15, dis##VU##MI_FTOI15, dis##VU##MI_MULAw , dis##VU##MI_CLIP , \
172 dis##VU##MI_MADDAi, dis##VU##MI_MSUBAi, disNULL , dis##VU##MI_NOP , \
173 disNULL , disNULL , disNULL , disNULL , \
174 disNULL , disNULL , disNULL , disNULL , \
175 disNULL , disNULL , disNULL , disNULL , \
176 disNULL , disNULL , disNULL , disNULL , \
177 disNULL , disNULL , disNULL , disNULL , \
178 }; \
179 \
180 MakeDisF(dis##VU##_UPPER_FD_00, dis##VU##_UPPER_FD_00_TABLE[_Fd_] DisFInterfaceN) \
181 MakeDisF(dis##VU##_UPPER_FD_01, dis##VU##_UPPER_FD_01_TABLE[_Fd_] DisFInterfaceN) \
182 MakeDisF(dis##VU##_UPPER_FD_10, dis##VU##_UPPER_FD_10_TABLE[_Fd_] DisFInterfaceN) \
183 MakeDisF(dis##VU##_UPPER_FD_11, dis##VU##_UPPER_FD_11_TABLE[_Fd_] DisFInterfaceN) \
184 \
185 TdisR5900F dis##VU##MicroU[] = { \
186 dis##VU##MI_ADDx , dis##VU##MI_ADDy , dis##VU##MI_ADDz , dis##VU##MI_ADDw, \
187 dis##VU##MI_SUBx , dis##VU##MI_SUBy , dis##VU##MI_SUBz , dis##VU##MI_SUBw, \
188 dis##VU##MI_MADDx , dis##VU##MI_MADDy , dis##VU##MI_MADDz , dis##VU##MI_MADDw, \
189 dis##VU##MI_MSUBx , dis##VU##MI_MSUBy , dis##VU##MI_MSUBz , dis##VU##MI_MSUBw, \
190 dis##VU##MI_MAXx , dis##VU##MI_MAXy , dis##VU##MI_MAXz , dis##VU##MI_MAXw, /* 0x10 */ \
191 dis##VU##MI_MINIx , dis##VU##MI_MINIy , dis##VU##MI_MINIz , dis##VU##MI_MINIw, \
192 dis##VU##MI_MULx , dis##VU##MI_MULy , dis##VU##MI_MULz , dis##VU##MI_MULw, \
193 dis##VU##MI_MULq , dis##VU##MI_MAXi , dis##VU##MI_MULi , dis##VU##MI_MINIi, \
194 dis##VU##MI_ADDq , dis##VU##MI_MADDq , dis##VU##MI_ADDi , dis##VU##MI_MADDi, /* 0x20 */ \
195 dis##VU##MI_SUBq , dis##VU##MI_MSUBq , dis##VU##MI_SUBi , dis##VU##MI_MSUBi, \
196 dis##VU##MI_ADD , dis##VU##MI_MADD , dis##VU##MI_MUL , dis##VU##MI_MAX, \
197 dis##VU##MI_SUB , dis##VU##MI_MSUB , dis##VU##MI_OPMSUB, dis##VU##MI_MINI, \
198 disNULL , disNULL , disNULL , disNULL , /* 0x30 */ \
199 disNULL , disNULL , disNULL , disNULL , \
200 disNULL , disNULL , disNULL , disNULL , \
201 dis##VU##_UPPER_FD_00, dis##VU##_UPPER_FD_01, dis##VU##_UPPER_FD_10, dis##VU##_UPPER_FD_11, \
202 }; \
203 \
204 \
205 MakeDisF(dis##VU##MicroUF, dis##VU##MicroU[code & 0x3f] DisFInterfaceN) \
206

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