/[pcsx2_0.9.7]/trunk/pcsx2/DebugTools/DisR3000A.cpp
ViewVC logotype

Contents of /trunk/pcsx2/DebugTools/DisR3000A.cpp

Parent Directory Parent Directory | Revision Log Revision Log


Revision 10 - (show annotations) (download)
Mon Sep 6 11:40:06 2010 UTC (9 years, 5 months ago) by william
File size: 16199 byte(s)
exported r3113 from ./upstream/trunk
1 /* PCSX2 - PS2 Emulator for PCs
2 * Copyright (C) 2002-2010 PCSX2 Dev Team
3 *
4 * PCSX2 is free software: you can redistribute it and/or modify it under the terms
5 * of the GNU Lesser General Public License as published by the Free Software Found-
6 * ation, either version 3 of the License, or (at your option) any later version.
7 *
8 * PCSX2 is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
9 * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
10 * PURPOSE. See the GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License along with PCSX2.
13 * If not, see <http://www.gnu.org/licenses/>.
14 */
15
16
17 #include "PrecompiledHeader.h"
18
19 #include "R3000A.h"
20 #include "Debug.h"
21
22 namespace R3000A
23 {
24 static char ostr[1024];
25
26 // Names of registers
27 const char * const disRNameGPR[] = {
28 "r0", "at", "v0", "v1", "a0", "a1","a2", "a3",
29 "t0", "t1", "t2", "t3", "t4", "t5","t6", "t7",
30 "s0", "s1", "s2", "s3", "s4", "s5","s6", "s7",
31 "t8", "t9", "k0", "k1", "gp", "sp","fp", "ra"};
32
33 const char * const disRNameCP0[] = {
34 "Index" , "Random" , "EntryLo0", "EntryLo1", "Context" , "PageMask" , "Wired" , "*Check me*",
35 "BadVAddr" , "Count" , "EntryHi" , "Compare" , "Status" , "Cause" , "ExceptPC" , "PRevID" ,
36 "Config" , "LLAddr" , "WatchLo" , "WatchHi" , "XContext", "*RES*" , "*RES*" , "*RES*" ,
37 "*RES*" , "*RES* " , "PErr" , "CacheErr", "TagLo" , "TagHi" , "ErrorEPC" , "*RES*" };
38
39 // Type definition of our functions
40
41 typedef char* (*TdisR3000AF)(u32 code, u32 pc);
42
43 // These macros are used to assemble the disassembler functions
44 #define MakeDisFg(fn, b) char* fn(u32 code, u32 pc) { b; return ostr; }
45 #define MakeDisF(fn, b) \
46 static char* fn(u32 code, u32 pc) { \
47 sprintf (ostr, "%8.8lx %8.8lx:", pc, code); \
48 b; /*ostr[(strlen(ostr) - 1)] = 0;*/ return ostr; \
49 }
50
51
52 #undef _Funct_
53 #undef _Rd_
54 #undef _Rt_
55 #undef _Rs_
56 #undef _Sa_
57 #undef _Im_
58 #undef _Target_
59
60 #define _Funct_ ((code ) & 0x3F) // The funct part of the instruction register
61 #define _Rd_ ((code >> 11) & 0x1F) // The rd part of the instruction register
62 #define _Rt_ ((code >> 16) & 0x1F) // The rt part of the instruction register
63 #define _Rs_ ((code >> 21) & 0x1F) // The rs part of the instruction register
64 #define _Sa_ ((code >> 6) & 0x1F) // The sa part of the instruction register
65 #define _Im_ ( code & 0xFFFF) // The immediate part of the instruction register
66
67 #define _Target_ ((pc & 0xf0000000) + ((code & 0x03ffffff) * 4))
68 #define _Branch_ (pc + 4 + ((short)_Im_ * 4))
69 #define _OfB_ _Im_, _nRs_
70
71 #define dName(i) sprintf(ostr, "%s %-7s,", ostr, i)
72 #define dGPR(i) sprintf(ostr, "%s %8.8lx (%s),", ostr, psxRegs.GPR.r[i], disRNameGPR[i])
73 #define dCP0(i) sprintf(ostr, "%s %8.8lx (%s),", ostr, psxRegs.CP0.r[i], disRNameCP0[i])
74 #define dHI() sprintf(ostr, "%s %8.8lx (%s),", ostr, psxRegs.GPR.n.hi, "hi")
75 #define dLO() sprintf(ostr, "%s %8.8lx (%s),", ostr, psxRegs.GPR.n.lo, "lo")
76 #define dImm() sprintf(ostr, "%s %4.4lx (%ld),", ostr, _Im_, _Im_)
77 #define dTarget() sprintf(ostr, "%s %8.8lx,", ostr, _Target_)
78 #define dSa() sprintf(ostr, "%s %2.2lx (%ld),", ostr, _Sa_, _Sa_)
79 #define dOfB() sprintf(ostr, "%s %4.4lx (%8.8lx (%s)),", ostr, _Im_, psxRegs.GPR.r[_Rs_], disRNameGPR[_Rs_])
80 #define dOffset() sprintf(ostr, "%s %8.8lx,", ostr, _Branch_)
81 #define dCode() sprintf(ostr, "%s %8.8lx,", ostr, (code >> 6) & 0xffffff)
82
83 /*********************************************************
84 * Arithmetic with immediate operand *
85 * Format: OP rt, rs, immediate *
86 *********************************************************/
87 MakeDisF(disADDI, dName("ADDI"); dGPR(_Rt_); dGPR(_Rs_); dImm();)
88 MakeDisF(disADDIU, dName("ADDIU"); dGPR(_Rt_); dGPR(_Rs_); dImm();)
89 MakeDisF(disANDI, dName("ANDI"); dGPR(_Rt_); dGPR(_Rs_); dImm();)
90 MakeDisF(disORI, dName("ORI"); dGPR(_Rt_); dGPR(_Rs_); dImm();)
91 MakeDisF(disSLTI, dName("SLTI"); dGPR(_Rt_); dGPR(_Rs_); dImm();)
92 MakeDisF(disSLTIU, dName("SLTIU"); dGPR(_Rt_); dGPR(_Rs_); dImm();)
93 MakeDisF(disXORI, dName("XORI"); dGPR(_Rt_); dGPR(_Rs_); dImm();)
94
95 /*********************************************************
96 * Register arithmetic *
97 * Format: OP rd, rs, rt *
98 *********************************************************/
99 MakeDisF(disADD, dName("ADD"); dGPR(_Rd_); dGPR(_Rs_); dGPR(_Rt_);)
100 MakeDisF(disADDU, dName("ADDU"); dGPR(_Rd_); dGPR(_Rs_); dGPR(_Rt_);)
101 MakeDisF(disAND, dName("AND"); dGPR(_Rd_); dGPR(_Rs_); dGPR(_Rt_);)
102 MakeDisF(disNOR, dName("NOR"); dGPR(_Rd_); dGPR(_Rs_); dGPR(_Rt_);)
103 MakeDisF(disOR, dName("OR"); dGPR(_Rd_); dGPR(_Rs_); dGPR(_Rt_);)
104 MakeDisF(disSLT, dName("SLT"); dGPR(_Rd_); dGPR(_Rs_); dGPR(_Rt_);)
105 MakeDisF(disSLTU, dName("SLTU"); dGPR(_Rd_); dGPR(_Rs_); dGPR(_Rt_);)
106 MakeDisF(disSUB, dName("SUB"); dGPR(_Rd_); dGPR(_Rs_); dGPR(_Rt_);)
107 MakeDisF(disSUBU, dName("SUBU"); dGPR(_Rd_); dGPR(_Rs_); dGPR(_Rt_);)
108 MakeDisF(disXOR, dName("XOR"); dGPR(_Rd_); dGPR(_Rs_); dGPR(_Rt_);)
109
110 /*********************************************************
111 * Register arithmetic & Register trap logic *
112 * Format: OP rs, rt *
113 *********************************************************/
114 MakeDisF(disDIV, dName("DIV"); dGPR(_Rs_); dGPR(_Rt_);)
115 MakeDisF(disDIVU, dName("DIVU"); dGPR(_Rs_); dGPR(_Rt_);)
116 MakeDisF(disMULT, dName("MULT"); dGPR(_Rs_); dGPR(_Rt_);)
117 MakeDisF(disMULTU, dName("MULTU"); dGPR(_Rs_); dGPR(_Rt_);)
118
119 /*********************************************************
120 * Register branch logic *
121 * Format: OP rs, offset *
122 *********************************************************/
123 MakeDisF(disBGEZ, dName("BGEZ"); dGPR(_Rs_); dOffset();)
124 MakeDisF(disBGEZAL, dName("BGEZAL"); dGPR(_Rs_); dOffset();)
125 MakeDisF(disBGTZ, dName("BGTZ"); dGPR(_Rs_); dOffset();)
126 MakeDisF(disBLEZ, dName("BLEZ"); dGPR(_Rs_); dOffset();)
127 MakeDisF(disBLTZ, dName("BLTZ"); dGPR(_Rs_); dOffset();)
128 MakeDisF(disBLTZAL, dName("BLTZAL"); dGPR(_Rs_); dOffset();)
129
130 /*********************************************************
131 * Shift arithmetic with constant shift *
132 * Format: OP rd, rt, sa *
133 *********************************************************/
134 MakeDisF(disSLL, if (code) { dName("SLL"); dGPR(_Rd_); dGPR(_Rt_); dSa(); } else { dName("NOP"); })
135 MakeDisF(disSRA, dName("SRA"); dGPR(_Rd_); dGPR(_Rt_); dSa();)
136 MakeDisF(disSRL, dName("SRL"); dGPR(_Rd_); dGPR(_Rt_); dSa();)
137
138 /*********************************************************
139 * Shift arithmetic with variant register shift *
140 * Format: OP rd, rt, rs *
141 *********************************************************/
142 MakeDisF(disSLLV, dName("SLLV"); dGPR(_Rd_); dGPR(_Rt_); dGPR(_Rs_);)
143 MakeDisF(disSRAV, dName("SRAV"); dGPR(_Rd_); dGPR(_Rt_); dGPR(_Rs_);)
144 MakeDisF(disSRLV, dName("SRLV"); dGPR(_Rd_); dGPR(_Rt_); dGPR(_Rs_);)
145
146 /*********************************************************
147 * Load higher 16 bits of the first word in GPR with imm *
148 * Format: OP rt, immediate *
149 *********************************************************/
150 MakeDisF(disLUI, dName("LUI"); dGPR(_Rt_); dImm();)
151
152 /*********************************************************
153 * Move from HI/LO to GPR *
154 * Format: OP rd *
155 *********************************************************/
156 MakeDisF(disMFHI, dName("MFHI"); dGPR(_Rd_); dHI();)
157 MakeDisF(disMFLO, dName("MFLO"); dGPR(_Rd_); dLO();)
158
159 /*********************************************************
160 * Move from GPR to HI/LO *
161 * Format: OP rd *
162 *********************************************************/
163 MakeDisF(disMTHI, dName("MTHI"); dHI(); dGPR(_Rs_);)
164 MakeDisF(disMTLO, dName("MTLO"); dLO(); dGPR(_Rs_);)
165
166 /*********************************************************
167 * Special purpose instructions *
168 * Format: OP *
169 *********************************************************/
170 MakeDisF(disBREAK, dName("BREAK"))
171 MakeDisF(disRFE, dName("RFE"))
172 MakeDisF(disSYSCALL, dName("SYSCALL"))
173
174
175
176 MakeDisF(disRTPS, dName("RTPS"))
177 MakeDisF(disOP , dName("OP"))
178 MakeDisF(disNCLIP, dName("NCLIP"))
179 MakeDisF(disDPCS, dName("DPCS"))
180 MakeDisF(disINTPL, dName("INTPL"))
181 MakeDisF(disMVMVA, dName("MVMVA"))
182 MakeDisF(disNCDS , dName("NCDS"))
183 MakeDisF(disCDP , dName("CDP"))
184 MakeDisF(disNCDT , dName("NCDT"))
185 MakeDisF(disNCCS , dName("NCCS"))
186 MakeDisF(disCC , dName("CC"))
187 MakeDisF(disNCS , dName("NCS"))
188 MakeDisF(disNCT , dName("NCT"))
189 MakeDisF(disSQR , dName("SQR"))
190 MakeDisF(disDCPL , dName("DCPL"))
191 MakeDisF(disDPCT , dName("DPCT"))
192 MakeDisF(disAVSZ3, dName("AVSZ3"))
193 MakeDisF(disAVSZ4, dName("AVSZ4"))
194 MakeDisF(disRTPT , dName("RTPT"))
195 MakeDisF(disGPF , dName("GPF"))
196 MakeDisF(disGPL , dName("GPL"))
197 MakeDisF(disNCCT , dName("NCCT"))
198
199 MakeDisF(disMFC2, dName("MFC2"); dGPR(_Rt_);)
200 MakeDisF(disCFC2, dName("CFC2"); dGPR(_Rt_);)
201 MakeDisF(disMTC2, dName("MTC2"))
202 MakeDisF(disCTC2, dName("CTC2"))
203
204 /*********************************************************
205 * Register branch logic *
206 * Format: OP rs, rt, offset *
207 *********************************************************/
208 MakeDisF(disBEQ, dName("BEQ"); dGPR(_Rs_); dGPR(_Rt_); dOffset();)
209 MakeDisF(disBNE, dName("BNE"); dGPR(_Rs_); dGPR(_Rt_); dOffset();)
210
211 /*********************************************************
212 * Jump to target *
213 * Format: OP target *
214 *********************************************************/
215 MakeDisF(disJ, dName("J"); dTarget();)
216 MakeDisF(disJAL, dName("JAL"); dTarget(); dGPR(31);)
217
218 /*********************************************************
219 * Register jump *
220 * Format: OP rs, rd *
221 *********************************************************/
222 MakeDisF(disJR, dName("JR"); dGPR(_Rs_);)
223 MakeDisF(disJALR, dName("JALR"); dGPR(_Rs_); dGPR(_Rd_))
224
225 /*********************************************************
226 * Load and store for GPR *
227 * Format: OP rt, offset(base) *
228 *********************************************************/
229 MakeDisF(disLB, dName("LB"); dGPR(_Rt_); dOfB();)
230 MakeDisF(disLBU, dName("LBU"); dGPR(_Rt_); dOfB();)
231 MakeDisF(disLH, dName("LH"); dGPR(_Rt_); dOfB();)
232 MakeDisF(disLHU, dName("LHU"); dGPR(_Rt_); dOfB();)
233 MakeDisF(disLW, dName("LW"); dGPR(_Rt_); dOfB();)
234 MakeDisF(disLWL, dName("LWL"); dGPR(_Rt_); dOfB();)
235 MakeDisF(disLWR, dName("LWR"); dGPR(_Rt_); dOfB();)
236 MakeDisF(disLWC2, dName("LWC2"); dGPR(_Rt_); dOfB();)
237 MakeDisF(disSB, dName("SB"); dGPR(_Rt_); dOfB();)
238 MakeDisF(disSH, dName("SH"); dGPR(_Rt_); dOfB();)
239 MakeDisF(disSW, dName("SW"); dGPR(_Rt_); dOfB();)
240 MakeDisF(disSWL, dName("SWL"); dGPR(_Rt_); dOfB();)
241 MakeDisF(disSWR, dName("SWR"); dGPR(_Rt_); dOfB();)
242 MakeDisF(disSWC2, dName("SWC2"); dGPR(_Rt_); dOfB();)
243
244 /*********************************************************
245 * Moves between GPR and COPx *
246 * Format: OP rt, fs *
247 *********************************************************/
248 MakeDisF(disMFC0, dName("MFC0"); dGPR(_Rt_); dCP0(_Rd_);)
249 MakeDisF(disMTC0, dName("MTC0"); dCP0(_Rd_); dGPR(_Rt_);)
250 MakeDisF(disCFC0, dName("CFC0"); dGPR(_Rt_); dCP0(_Rd_);)
251 MakeDisF(disCTC0, dName("CTC0"); dCP0(_Rd_); dGPR(_Rt_);)
252
253 /*********************************************************
254 * Unknow instruction (would generate an exception) *
255 * Format: ? *
256 *********************************************************/
257 MakeDisF(disNULL, dName("*** Bad OP ***");)
258
259
260 TdisR3000AF disR3000A_SPECIAL[] = { // Subset of disSPECIAL
261 disSLL , disNULL , disSRL , disSRA , disSLLV , disNULL , disSRLV , disSRAV ,
262 disJR , disJALR , disNULL, disNULL, disSYSCALL, disBREAK , disNULL , disNULL ,
263 disMFHI, disMTHI , disMFLO, disMTLO, disNULL , disNULL , disNULL , disNULL ,
264 disMULT, disMULTU, disDIV , disDIVU, disNULL , disNULL , disNULL , disNULL ,
265 disADD , disADDU , disSUB , disSUBU, disAND , disOR , disXOR , disNOR ,
266 disNULL, disNULL , disSLT , disSLTU, disNULL , disNULL , disNULL , disNULL ,
267 disNULL, disNULL , disNULL, disNULL, disNULL , disNULL , disNULL , disNULL ,
268 disNULL, disNULL , disNULL, disNULL, disNULL , disNULL , disNULL , disNULL};
269
270 MakeDisF(disSPECIAL, disR3000A_SPECIAL[_Funct_](code, pc))
271
272 TdisR3000AF disR3000A_BCOND[] = { // Subset of disBCOND
273 disBLTZ , disBGEZ , disNULL, disNULL, disNULL, disNULL, disNULL, disNULL,
274 disNULL , disNULL , disNULL, disNULL, disNULL, disNULL, disNULL, disNULL,
275 disBLTZAL, disBGEZAL, disNULL, disNULL, disNULL, disNULL, disNULL, disNULL,
276 disNULL , disNULL , disNULL, disNULL, disNULL, disNULL, disNULL, disNULL};
277
278 MakeDisF(disBCOND, disR3000A_BCOND[_Rt_](code, pc))
279
280 TdisR3000AF disR3000A_COP0[] = { // Subset of disCOP0
281 disMFC0, disNULL, disCFC0, disNULL, disMTC0, disNULL, disCTC0, disNULL,
282 disNULL, disNULL, disNULL, disNULL, disNULL, disNULL, disNULL, disNULL,
283 disRFE , disNULL, disNULL, disNULL, disNULL, disNULL, disNULL, disNULL,
284 disNULL, disNULL, disNULL, disNULL, disNULL, disNULL, disNULL, disNULL};
285
286 MakeDisF(disCOP0, disR3000A_COP0[_Rs_](code, pc))
287
288 TdisR3000AF disR3000A_BASIC[] = { // Subset of disBASIC (based on rs)
289 disMFC2, disNULL, disCFC2, disNULL, disMTC2, disNULL, disCTC2, disNULL,
290 disNULL, disNULL, disNULL, disNULL, disNULL, disNULL, disNULL, disNULL,
291 disNULL, disNULL, disNULL, disNULL, disNULL, disNULL, disNULL, disNULL,
292 disNULL, disNULL, disNULL, disNULL, disNULL, disNULL, disNULL, disNULL};
293
294 MakeDisF(disBASIC, disR3000A_BASIC[_Rs_](code, pc))
295
296 TdisR3000AF disR3000A_COP2[] = { // Subset of disR3000F_COP2 (based on funct)
297 disBASIC, disRTPS , disNULL , disNULL , disNULL, disNULL , disNCLIP, disNULL,
298 disNULL , disNULL , disNULL , disNULL , disOP , disNULL , disNULL , disNULL,
299 disDPCS , disINTPL, disMVMVA, disNCDS , disCDP , disNULL , disNCDT , disNULL,
300 disNULL , disNULL , disNULL , disNCCS , disCC , disNULL , disNCS , disNULL,
301 disNCT , disNULL , disNULL , disNULL , disNULL, disNULL , disNULL , disNULL,
302 disSQR , disDCPL , disDPCT , disNULL , disNULL, disAVSZ3, disAVSZ4, disNULL,
303 disRTPT , disNULL , disNULL , disNULL , disNULL, disNULL , disNULL , disNULL,
304 disNULL , disNULL , disNULL , disNULL , disNULL, disGPF , disGPL , disNCCT };
305
306 MakeDisF(disCOP2, disR3000A_COP2[_Funct_](code, pc))
307
308 TdisR3000AF disR3000A[] = {
309 disSPECIAL , disBCOND , disJ , disJAL , disBEQ , disBNE , disBLEZ , disBGTZ ,
310 disADDI , disADDIU , disSLTI , disSLTIU, disANDI, disORI , disXORI , disLUI ,
311 disCOP0 , disNULL , disCOP2 , disNULL , disNULL, disNULL, disNULL , disNULL ,
312 disNULL , disNULL , disNULL , disNULL , disNULL, disNULL, disNULL , disNULL ,
313 disLB , disLH , disLWL , disLW , disLBU , disLHU , disLWR , disNULL ,
314 disSB , disSH , disSWL , disSW , disNULL, disNULL, disSWR , disNULL ,
315 disNULL , disNULL , disLWC2 , disNULL , disNULL, disNULL, disNULL , disNULL ,
316 disNULL , disNULL , disSWC2 , disNULL , disNULL, disNULL, disNULL , disNULL };
317
318 MakeDisFg(disR3000AF, disR3000A[code >> 26](code, pc))
319
320 }

  ViewVC Help
Powered by ViewVC 1.1.22