/[pcsx2_0.9.7]/trunk/pcsx2/DebugTools/DisASM.h
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Contents of /trunk/pcsx2/DebugTools/DisASM.h

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Revision 31 - (show annotations) (download)
Tue Sep 7 03:24:11 2010 UTC (9 years, 9 months ago) by william
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committing r3113 initial commit again...
1 /* PCSX2 - PS2 Emulator for PCs
2 * Copyright (C) 2002-2010 PCSX2 Dev Team
3 *
4 * PCSX2 is free software: you can redistribute it and/or modify it under the terms
5 * of the GNU Lesser General Public License as published by the Free Software Found-
6 * ation, either version 3 of the License, or (at your option) any later version.
7 *
8 * PCSX2 is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
9 * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
10 * PURPOSE. See the GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License along with PCSX2.
13 * If not, see <http://www.gnu.org/licenses/>.
14 */
15
16 #include <stdio.h>
17 #include <string.h>
18
19 //DECODE PROCUDURES
20
21 //cop0
22 #define DECODE_FS (DECODE_RD)
23 #define DECODE_FT (DECODE_RT)
24 #define DECODE_FD (DECODE_SA)
25 ///********
26
27 #define DECODE_FUNCTION ((cpuRegs.code) & 0x3F)
28 #define DECODE_RD ((cpuRegs.code >> 11) & 0x1F) // The rd part of the instruction register
29 #define DECODE_RT ((cpuRegs.code >> 16) & 0x1F) // The rt part of the instruction register
30 #define DECODE_RS ((cpuRegs.code >> 21) & 0x1F) // The rs part of the instruction register
31 #define DECODE_SA ((cpuRegs.code >> 6) & 0x1F) // The sa part of the instruction register
32 #define DECODE_IMMED ( cpuRegs.code & 0xFFFF) // The immediate part of the instruction register
33 #define DECODE_OFFSET ((((short)DECODE_IMMED * 4) + opcode_addr + 4))
34 #define DECODE_JUMP (opcode_addr & 0xf0000000)|((cpuRegs.code&0x3ffffff)<<2)
35 #define DECODE_SYSCALL ((opcode_addr & 0x03FFFFFF) >> 6)
36 #define DECODE_BREAK (DECODE_SYSCALL)
37 #define DECODE_C0BC ((cpuRegs.code >> 16) & 0x03)
38 #define DECODE_C1BC ((cpuRegs.code >> 16) & 0x03)
39 #define DECODE_C2BC ((cpuRegs.code >> 16) & 0x03)
40
41 //IOP
42
43 #define DECODE_RD_IOP ((psxRegs.code >> 11) & 0x1F)
44 #define DECODE_RT_IOP ((psxRegs.code >> 16) & 0x1F)
45 #define DECODE_RS_IOP ((psxRegs.code >> 21) & 0x1F)
46 #define DECODE_IMMED_IOP ( psxRegs.code & 0xFFFF)
47 #define DECODE_SA_IOP ((psxRegs.code >> 6) & 0x1F)
48 #define DECODE_FS_IOP (DECODE_RD_IOP)
49

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