/[pcsx2_0.9.7]/trunk/pcsx2/Cache.cpp
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Annotation of /trunk/pcsx2/Cache.cpp

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Revision 401 - (hide annotations) (download)
Fri Feb 25 17:31:09 2011 UTC (9 years, 4 months ago) by william
File size: 16429 byte(s)
Auto Commited Import of: pcsx2-0.9.7-DEBUG (upstream: v0.9.7.4358 local: v0.9.7.313-latest) in ./trunk
1 william 31 /* PCSX2 - PS2 Emulator for PCs
2     * Copyright (C) 2002-2010 PCSX2 Dev Team
3     *
4     * PCSX2 is free software: you can redistribute it and/or modify it under the terms
5     * of the GNU Lesser General Public License as published by the Free Software Found-
6     * ation, either version 3 of the License, or (at your option) any later version.
7     *
8     * PCSX2 is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
9     * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
10     * PURPOSE. See the GNU General Public License for more details.
11     *
12     * You should have received a copy of the GNU General Public License along with PCSX2.
13     * If not, see <http://www.gnu.org/licenses/>.
14     */
15    
16    
17     #include "PrecompiledHeader.h"
18     #include "Common.h"
19     #include "Cache.h"
20 william 401 #include "vtlb.h"
21 william 31 _cacheS pCache[64];
22    
23 william 401 #define DIRTY_FLAG 0x40
24     #define VALID_FLAG 0x20
25     #define LRF_FLAG 0x10
26     #define LOCK_FLAG 0x8
27 william 31
28 william 401 using namespace R5900;
29     using namespace vtlb_private;
30    
31    
32    
33     int getFreeCache(u32 mem, int mode, int * way ) {
34 william 31 int number;
35     int i = (mem >> 6) & 0x3F;
36 william 401 u32 vmv=vtlbdata.vmap[mem>>VTLB_PAGE_BITS];
37     s32 ppf=mem+vmv;
38 william 31
39 william 401 u32 hand=(u8)vmv;
40     u32 paddr=ppf-hand+0x80000000;
41 william 31
42 william 401 if((cpuRegs.CP0.n.Config & 0x10000) == 0) DevCon.Warning("Cache off!");
43    
44     if ((pCache[i].tag[0] & ~0xFFF) == (paddr & ~0xFFF) && (pCache[i].tag[0] & VALID_FLAG))
45 william 31 {
46     *way = 0;
47 william 401 if(pCache[i].tag[0] & LOCK_FLAG) DevCon.Warning("Index %x Way %x Locked!!", i, 0);
48 william 31 return i;
49     }
50 william 401 else if((pCache[i].tag[1] & ~0xFFF) == (paddr & ~0xFFF) && (pCache[i].tag[1] & VALID_FLAG))
51 william 31 {
52     *way = 1;
53 william 401 if(pCache[i].tag[1] & LOCK_FLAG) DevCon.Warning("Index %x Way %x Locked!!", i, 1);
54 william 31 return i;
55     }
56    
57 william 401
58    
59 william 31 number = ((pCache[i].tag[0]>>4) & 1) ^ ((pCache[i].tag[1]>>4) & 1);
60 william 401
61 william 31
62 william 401 ppf = (ppf & ~0x3F) ;
63     if((pCache[i].tag[number] & (DIRTY_FLAG|VALID_FLAG)) == (DIRTY_FLAG|VALID_FLAG)) // Dirty
64     {
65     s32 oldppf = (pCache[i].tag[number] & ~0xf0000fff) + (mem & 0xFC0) + 0x20000000;
66    
67     CACHE_LOG("Dirty cache fill! PPF %x", oldppf);
68     *reinterpret_cast<mem64_t*>(oldppf) = pCache[i].data[number][0].b8._u64[0];
69     *reinterpret_cast<mem64_t*>(oldppf+8) = pCache[i].data[number][0].b8._u64[1];
70     *reinterpret_cast<mem64_t*>(oldppf+16) = pCache[i].data[number][1].b8._u64[0];
71     *reinterpret_cast<mem64_t*>(oldppf+24) = pCache[i].data[number][1].b8._u64[1];
72     *reinterpret_cast<mem64_t*>(oldppf+32) = pCache[i].data[number][2].b8._u64[0];
73     *reinterpret_cast<mem64_t*>(oldppf+40) = pCache[i].data[number][2].b8._u64[1];
74     *reinterpret_cast<mem64_t*>(oldppf+48) = pCache[i].data[number][3].b8._u64[0];
75     *reinterpret_cast<mem64_t*>(oldppf+56) = pCache[i].data[number][3].b8._u64[1];
76     pCache[i].tag[number] &= ~DIRTY_FLAG;
77 william 31 }
78 william 401
79    
80     pCache[i].data[number][0].b8._u64[0] = *(mem64_t*)(ppf);
81     pCache[i].data[number][0].b8._u64[1] = *(mem64_t*)(ppf+8);
82     pCache[i].data[number][1].b8._u64[0] = *(mem64_t*)(ppf+16);
83     pCache[i].data[number][1].b8._u64[1] = *(mem64_t*)(ppf+24);
84     pCache[i].data[number][2].b8._u64[0] = *(mem64_t*)(ppf+32);
85     pCache[i].data[number][2].b8._u64[1] = *(mem64_t*)(ppf+40);
86     pCache[i].data[number][3].b8._u64[0] = *(mem64_t*)(ppf+48);
87     pCache[i].data[number][3].b8._u64[1] = *(mem64_t*)(ppf+56);
88 william 31
89 william 401 *way = number;
90     pCache[i].tag[number] |= VALID_FLAG;
91     pCache[i].tag[number] &= 0xFFF;
92     pCache[i].tag[number] |= paddr & ~0xFFF;
93 william 31
94 william 401 if(pCache[i].tag[number] & LRF_FLAG)
95     pCache[i].tag[number] &= ~LRF_FLAG;
96 william 31 else
97 william 401 pCache[i].tag[number] |= LRF_FLAG;
98 william 31
99 william 401
100 william 31 return i;
101 william 401
102 william 31 }
103    
104     void writeCache8(u32 mem, u8 value) {
105     int i, number;
106 william 401 u32 vmv=vtlbdata.vmap[mem>>VTLB_PAGE_BITS];
107     s32 ppf=(mem+vmv) & ~0x3f;
108 william 31 i = getFreeCache(mem,1,&number);
109 william 401 CACHE_LOG("writeCache8 %8.8x adding to %d, way %d, value %x", mem, i,number,value);
110     pCache[i].tag[number] |= DIRTY_FLAG; // Set Dirty Bit if mode == write
111     pCache[i].data[number][(mem>>4) & 0x3].b8._u8[(mem&0xf)] = value;
112 william 31 }
113    
114     void writeCache16(u32 mem, u16 value) {
115     int i, number;
116 william 401 u32 vmv=vtlbdata.vmap[mem>>VTLB_PAGE_BITS];
117     s32 ppf=(mem+vmv) & ~0x3f;
118 william 31 i = getFreeCache(mem,1,&number);
119 william 401 CACHE_LOG("writeCache16 %8.8x adding to %d, way %d, value %x", mem, i,number,value);
120     pCache[i].tag[number] |= DIRTY_FLAG; // Set Dirty Bit if mode == write
121     pCache[i].data[number][(mem>>4) & 0x3].b8._u16[(mem&0xf)>>1] = value;
122 william 31 }
123    
124     void writeCache32(u32 mem, u32 value) {
125     int i, number;
126 william 401 u32 vmv=vtlbdata.vmap[mem>>VTLB_PAGE_BITS];
127     s32 ppf=(mem+vmv) & ~0x3f;
128     i = getFreeCache(mem,1,&number);
129     CACHE_LOG("writeCache32 %8.8x adding to %d, way %d, value %x", mem, i,number,value);
130     pCache[i].tag[number] |= DIRTY_FLAG; // Set Dirty Bit if mode == write
131     pCache[i].data[number][(mem>>4) & 0x3].b8._u32[(mem&0xf)>>2] = value;
132     }
133 william 31
134 william 401 void writeCache64(u32 mem, const u64 value) {
135     int i, number;
136     u32 vmv=vtlbdata.vmap[mem>>VTLB_PAGE_BITS];
137     s32 ppf=(mem+vmv) & ~0x3f;
138 william 31 i = getFreeCache(mem,1,&number);
139 william 401 CACHE_LOG("writeCache64 %8.8x adding to %d, way %d, value %x", mem, i,number,value);
140     pCache[i].tag[number] |= DIRTY_FLAG; // Set Dirty Bit if mode == write
141     pCache[i].data[number][(mem>>4) & 0x3].b8._u64[(mem&0xf)>>3] = value;
142 william 31 }
143    
144 william 401 void writeCache128(u32 mem, const mem128_t* value){
145 william 31 int i, number;
146 william 401 u32 vmv=vtlbdata.vmap[mem>>VTLB_PAGE_BITS];
147     s32 ppf=(mem+vmv) & ~0x3f;
148 william 31 i = getFreeCache(mem,1,&number);
149 william 401 CACHE_LOG("writeCache128 %8.8x adding to %d way %x tag %x vallo = %x_%x valhi = %x_%x", mem, i, number, pCache[i].tag[number], value->lo, value->hi);
150     pCache[i].tag[number] |= DIRTY_FLAG; // Set Dirty Bit if mode == write
151     pCache[i].data[number][(mem>>4) & 0x3].b8._u64[0] = value->lo;
152     pCache[i].data[number][(mem>>4) & 0x3].b8._u64[1] = value->hi;
153 william 31 }
154    
155 william 401 u8 readCache8(u32 mem) {
156 william 31 int i, number;
157 william 401
158     i = getFreeCache(mem,0,&number);
159     CACHE_LOG("readCache %8.8x from %d, way %d QW %x u8 part %x Really Reading %x", mem, i,number, (mem >> 4) & 0x3, (mem&0xf)>>2, (u32)pCache[i].data[number][(mem >> 4) & 0x3].b8._u8[(mem&0xf)]);
160 william 31
161 william 401 return pCache[i].data[number][(mem >> 4) & 0x3].b8._u8[(mem&0xf)];
162 william 31 }
163    
164 william 401 u16 readCache16(u32 mem) {
165 william 31 int i, number;
166 william 401
167     i = getFreeCache(mem,0,&number);
168     CACHE_LOG("readCache %8.8x from %d, way %d QW %x u16 part %x Really Reading %x", mem, i,number, (mem >> 4) & 0x3, (mem&0xf)>>2, (u32)pCache[i].data[number][(mem >> 4) & 0x3].b8._u16[(mem&0xf)>>1]);
169 william 31
170 william 401 return pCache[i].data[number][(mem >> 4) & 0x3].b8._u16[(mem&0xf)>>1];
171     }
172    
173     u32 readCache32(u32 mem) {
174     int i, number;
175    
176 william 31 i = getFreeCache(mem,0,&number);
177 william 401 CACHE_LOG("readCache %8.8x from %d, way %d QW %x u32 part %x Really Reading %x", mem, i,number, (mem >> 4) & 0x3, (mem&0xf)>>2, (u32)pCache[i].data[number][(mem >> 4) & 0x3].b8._u32[(mem&0xf)>>2]);
178 william 31
179 william 401 return pCache[i].data[number][(mem >> 4) & 0x3].b8._u32[(mem&0xf)>>2];
180 william 31 }
181    
182 william 401 u64 readCache64(u32 mem) {
183     int i, number;
184    
185     i = getFreeCache(mem,0,&number);
186     CACHE_LOG("readCache %8.8x from %d, way %d QW %x u64 part %x Really Reading %x_%x", mem, i,number, (mem >> 4) & 0x3, (mem&0xf)>>2, pCache[i].data[number][(mem >> 4) & 0x3].b8._u64[(mem&0xf)>>3]);
187    
188     return pCache[i].data[number][(mem >> 4) & 0x3].b8._u64[(mem&0xf)>>3];
189     }
190    
191     namespace R5900 {
192     namespace Interpreter
193     {
194 william 31 namespace OpcodeImpl
195     {
196    
197     extern int Dcache;
198     void CACHE() {
199     u32 addr;
200 william 401
201 william 31 addr = cpuRegs.GPR.r[_Rs_].UL[0] + _Imm_;
202 william 401 // DevCon.Warning("cpuRegs.GPR.r[_Rs_].UL[0] = %x, IMM = %x RT = %x", cpuRegs.GPR.r[_Rs_].UL[0], _Imm_, _Rt_);
203     switch (_Rt_)
204     {
205     case 0x1a: //DHIN (Data Cache Hit Invalidate)
206 william 31 {
207     int index = (addr >> 6) & 0x3F;
208 william 401 int way = 0;
209     u32 pfnaddr = addr;
210     u32 vmv=vtlbdata.vmap[pfnaddr>>VTLB_PAGE_BITS];
211     s32 ppf=pfnaddr+vmv;
212     u32 hand=(u8)vmv;
213     u32 paddr=ppf-hand+0x80000000;
214 william 31
215 william 401 if((paddr & ~0xFFF) == (pCache[index].tag[0] & ~0xfff) && (pCache[index].tag[0] & VALID_FLAG))
216 william 31 {
217     way = 0;
218     }
219 william 401 else if((paddr & ~0xFFF) == (pCache[index].tag[1] & ~0xfff) && (pCache[index].tag[1] & VALID_FLAG))
220 william 31 {
221     way = 1;
222     }
223     else
224     {
225 william 401 CACHE_LOG("CACHE DHIN NO HIT addr %x, index %d, phys %x tag0 %x tag1 %x",addr,index, paddr, pCache[index].tag[0], pCache[index].tag[1]);
226 william 31 return;
227     }
228    
229 william 401 CACHE_LOG("CACHE DHIN addr %x, index %d, way %d, Flags %x OP %x",addr,index,way,pCache[index].tag[way] & 0x78, cpuRegs.code);
230 william 31
231 william 401 pCache[index].tag[way] &= LRF_FLAG;
232     pCache[index].data[way][0].b8._u64[0] = 0;
233     pCache[index].data[way][0].b8._u64[1] = 0;
234     pCache[index].data[way][1].b8._u64[0] = 0;
235     pCache[index].data[way][1].b8._u64[1] = 0;
236     pCache[index].data[way][2].b8._u64[0] = 0;
237     pCache[index].data[way][2].b8._u64[1] = 0;
238     pCache[index].data[way][3].b8._u64[0] = 0;
239     pCache[index].data[way][3].b8._u64[1] = 0;
240    
241 william 31 break;
242     }
243 william 401 case 0x18: //DHWBIN (Data Cache Hit WriteBack with Invalidate)
244 william 31 {
245     int index = (addr >> 6) & 0x3F;
246 william 401 int way = 0;
247     u32 pfnaddr = addr;
248     u32 vmv=vtlbdata.vmap[pfnaddr>>VTLB_PAGE_BITS];
249     s32 ppf=(pfnaddr+vmv) & ~0x3F;
250     u32 hand=(u8)vmv;
251     u32 paddr=ppf-hand+0x80000000;
252 william 31
253 william 401 if ((pCache[index].tag[0] & ~0xFFF) == (paddr & ~0xFFF) && (pCache[index].tag[0] & VALID_FLAG))
254 william 31 {
255     way = 0;
256     }
257 william 401 else if((pCache[index].tag[1] & ~0xFFF) == (paddr & ~0xFFF) && (pCache[index].tag[1] & VALID_FLAG))
258 william 31 {
259     way = 1;
260     }
261     else
262     {
263 william 401 CACHE_LOG("CACHE DHWBIN NO HIT addr %x, index %d, phys %x tag0 %x tag1 %x",addr,index, paddr, pCache[index].tag[0], pCache[index].tag[1]);
264 william 31 return;
265     }
266 william 401
267    
268     CACHE_LOG("CACHE DHWBIN addr %x, index %d, phys %x tag0 %x tag1 %x way %x",addr,index, paddr, pCache[index].tag[0], pCache[index].tag[1], way );
269 william 31
270 william 401 if((pCache[index].tag[way] & (DIRTY_FLAG|VALID_FLAG)) == (DIRTY_FLAG|VALID_FLAG)) // Dirty
271     {
272     CACHE_LOG("DHWBIN Dirty WriteBack PPF %x", ppf);
273 william 31
274 william 401 *reinterpret_cast<mem64_t*>(ppf) = pCache[index].data[way][0].b8._u64[0];
275     *reinterpret_cast<mem64_t*>(ppf+8) = pCache[index].data[way][0].b8._u64[1];
276     *reinterpret_cast<mem64_t*>(ppf+16) = pCache[index].data[way][1].b8._u64[0];
277     *reinterpret_cast<mem64_t*>(ppf+24) = pCache[index].data[way][1].b8._u64[1];
278     *reinterpret_cast<mem64_t*>(ppf+32) = pCache[index].data[way][2].b8._u64[0];
279     *reinterpret_cast<mem64_t*>(ppf+40) = pCache[index].data[way][2].b8._u64[1];
280     *reinterpret_cast<mem64_t*>(ppf+48) = pCache[index].data[way][3].b8._u64[0];
281     *reinterpret_cast<mem64_t*>(ppf+56) = pCache[index].data[way][3].b8._u64[1];
282 william 31 }
283    
284 william 401 pCache[index].tag[way] &= LRF_FLAG;
285 william 31
286 william 401 pCache[index].data[way][0].b8._u64[0] = 0;
287     pCache[index].data[way][0].b8._u64[1] = 0;
288     pCache[index].data[way][1].b8._u64[0] = 0;
289     pCache[index].data[way][1].b8._u64[1] = 0;
290     pCache[index].data[way][2].b8._u64[0] = 0;
291     pCache[index].data[way][2].b8._u64[1] = 0;
292     pCache[index].data[way][3].b8._u64[0] = 0;
293     pCache[index].data[way][3].b8._u64[1] = 0;
294    
295 william 31 break;
296     }
297 william 401 case 0x1c: //DHWOIN (Data Cache Hit WriteBack Without Invalidate)
298 william 31 {
299     int index = (addr >> 6) & 0x3F;
300 william 401 int way = 0;
301     u32 pfnaddr = (pCache[index].tag[way] & ~0xf0000fff) | (addr & 0xfc0);
302     u32 vmv=vtlbdata.vmap[pfnaddr>>VTLB_PAGE_BITS];
303     s32 ppf=(pfnaddr+vmv) & ~0x3F;
304     u32 hand=(u8)vmv;
305     u32 paddr=ppf-hand+0x80000000;
306    
307     CACHE_LOG("CACHE DHWOIN addr %x, index %d, way %d, Flags %x OP %x",addr,index,way,pCache[index].tag[way] & 0x78, cpuRegs.code);
308 william 31
309 william 401 if ((pCache[index].tag[0] & ~0xFFF) == (paddr & ~0xFFF) && (pCache[index].tag[0] & VALID_FLAG))
310 william 31 {
311     way = 0;
312     }
313 william 401 else if((pCache[index].tag[1] & ~0xFFF) == (paddr & ~0xFFF) && (pCache[index].tag[1] & VALID_FLAG))
314 william 31 {
315     way = 1;
316     }
317     else
318     {
319 william 401 CACHE_LOG("CACHE DHWOIN NO HIT addr %x, index %d, phys %x tag0 %x tag1 %x",addr,index, paddr, pCache[index].tag[0], pCache[index].tag[1]);
320 william 31 return;
321     }
322    
323 william 401 if((pCache[index].tag[way] & (DIRTY_FLAG|VALID_FLAG)) == (DIRTY_FLAG|VALID_FLAG)) // Dirty
324 william 31 {
325 william 401 CACHE_LOG("DHWOIN Dirty WriteBack! PPF %x", ppf);
326     *reinterpret_cast<mem64_t*>(ppf) = pCache[index].data[way][0].b8._u64[0];
327     *reinterpret_cast<mem64_t*>(ppf+8) = pCache[index].data[way][0].b8._u64[1];
328     *reinterpret_cast<mem64_t*>(ppf+16) = pCache[index].data[way][1].b8._u64[0];
329     *reinterpret_cast<mem64_t*>(ppf+24) = pCache[index].data[way][1].b8._u64[1];
330     *reinterpret_cast<mem64_t*>(ppf+32) = pCache[index].data[way][2].b8._u64[0];
331     *reinterpret_cast<mem64_t*>(ppf+40) = pCache[index].data[way][2].b8._u64[1];
332     *reinterpret_cast<mem64_t*>(ppf+48) = pCache[index].data[way][3].b8._u64[0];
333     *reinterpret_cast<mem64_t*>(ppf+56) = pCache[index].data[way][3].b8._u64[1];
334    
335     pCache[index].tag[way] &= ~DIRTY_FLAG;
336 william 31 }
337    
338     break;
339     }
340 william 401 case 0x16: //DXIN (Data Cache Index Invalidate)
341 william 31 {
342     int index = (addr >> 6) & 0x3F;
343     int way = addr & 0x1;
344    
345     CACHE_LOG("CACHE DXIN addr %x, index %d, way %d, flag %x\n",addr,index,way,pCache[index].tag[way] & 0x78);
346    
347 william 401 pCache[index].tag[way] &= LRF_FLAG;
348 william 31
349 william 401 pCache[index].data[way][0].b8._u64[0] = 0;
350     pCache[index].data[way][0].b8._u64[1] = 0;
351     pCache[index].data[way][1].b8._u64[0] = 0;
352     pCache[index].data[way][1].b8._u64[1] = 0;
353     pCache[index].data[way][2].b8._u64[0] = 0;
354     pCache[index].data[way][2].b8._u64[1] = 0;
355     pCache[index].data[way][3].b8._u64[0] = 0;
356     pCache[index].data[way][3].b8._u64[1] = 0;
357    
358     break;
359 william 31 }
360 william 401 case 0x11: //DXLDT (Data Cache Load Data into TagLo)
361 william 31 {
362     int index = (addr >> 6) & 0x3F;
363     int way = addr & 0x1;
364    
365 william 401 cpuRegs.CP0.n.TagLo = pCache[index].data[way][(addr>>4) & 0x3].b8._u32[(addr&0xf)>>2];
366 william 31
367 william 401 CACHE_LOG("CACHE DXLDT addr %x, index %d, way %d, DATA %x OP %x",addr,index,way,cpuRegs.CP0.r[28], cpuRegs.code);
368    
369 william 31 break;
370     }
371 william 401 case 0x10: //DXLTG (Data Cache Load Tag into TagLo)
372 william 31 {
373     int index = (addr >> 6) & 0x3F;
374     int way = addr & 0x1;
375 william 401
376     cpuRegs.CP0.n.TagLo = pCache[index].tag[way];
377 william 31
378 william 401 CACHE_LOG("CACHE DXLTG addr %x, index %d, way %d, DATA %x OP %x ",addr,index,way,cpuRegs.CP0.r[28], cpuRegs.code);
379 william 31
380     break;
381     }
382 william 401 case 0x13: //DXSDT (Data Cache Store 32bits from TagLo)
383 william 31 {
384     int index = (addr >> 6) & 0x3F;
385     int way = addr & 0x1;
386    
387 william 401 pCache[index].data[way][(addr>>4) & 0x3].b8._u32[(addr&0xf)>>2] = cpuRegs.CP0.n.TagLo;
388 william 31
389 william 401 CACHE_LOG("CACHE DXSDT addr %x, index %d, way %d, DATA %x OP %x",addr,index,way,cpuRegs.CP0.r[28], cpuRegs.code);
390    
391 william 31 break;
392     }
393 william 401 case 0x12: //DXSTG (Data Cache Store Tag from TagLo)
394 william 31 {
395     int index = (addr >> 6) & 0x3F;
396     int way = addr & 0x1;
397 william 401 pCache[index].tag[way] = cpuRegs.CP0.n.TagLo;
398 william 31
399 william 401 CACHE_LOG("CACHE DXSTG addr %x, index %d, way %d, DATA %x OP %x",addr,index,way,cpuRegs.CP0.r[28] & 0x6F, cpuRegs.code);
400 william 31
401     break;
402     }
403 william 401 case 0x14: //DXWBIN (Data Cache Index WriteBack Invalidate)
404 william 31 {
405     int index = (addr >> 6) & 0x3F;
406     int way = addr & 0x1;
407 william 401 u32 pfnaddr = (pCache[index].tag[way] & ~0xf0000fff) + (addr & 0xFC0);
408     u32 vmv=vtlbdata.vmap[pfnaddr >>VTLB_PAGE_BITS];
409     s32 ppf=pfnaddr+vmv;
410     u32 hand=(u8)vmv;
411     u32 paddr=ppf-hand+0x80000000;
412 william 31
413 william 401 CACHE_LOG("CACHE DXWBIN addr %x, index %d, way %d, Flags %x Paddr %x tag %x",addr,index,way,pCache[index].tag[way] & 0x78, paddr, pCache[index].tag[way]);
414     if((pCache[index].tag[way] & (DIRTY_FLAG|VALID_FLAG)) == (DIRTY_FLAG|VALID_FLAG)) // Dirty
415     {
416     ppf = (ppf & 0x0fffffff) + 0x20000000;
417     CACHE_LOG("DXWBIN Dirty WriteBack! PPF %x", ppf);
418 william 31
419 william 401 *reinterpret_cast<mem64_t*>(ppf) = pCache[index].data[way][0].b8._u64[0];
420     *reinterpret_cast<mem64_t*>(ppf+8) = pCache[index].data[way][0].b8._u64[1];
421     *reinterpret_cast<mem64_t*>(ppf+16) = pCache[index].data[way][1].b8._u64[0];
422     *reinterpret_cast<mem64_t*>(ppf+24) = pCache[index].data[way][1].b8._u64[1];
423     *reinterpret_cast<mem64_t*>(ppf+32) = pCache[index].data[way][2].b8._u64[0];
424     *reinterpret_cast<mem64_t*>(ppf+40) = pCache[index].data[way][2].b8._u64[1];
425     *reinterpret_cast<mem64_t*>(ppf+48) = pCache[index].data[way][3].b8._u64[0];
426     *reinterpret_cast<mem64_t*>(ppf+56) = pCache[index].data[way][3].b8._u64[1];
427 william 31
428     }
429    
430 william 401 pCache[index].tag[way] &= LRF_FLAG;
431    
432     pCache[index].data[way][0].b8._u64[0] = 0;
433     pCache[index].data[way][0].b8._u64[1] = 0;
434     pCache[index].data[way][1].b8._u64[0] = 0;
435     pCache[index].data[way][1].b8._u64[1] = 0;
436     pCache[index].data[way][2].b8._u64[0] = 0;
437     pCache[index].data[way][2].b8._u64[1] = 0;
438     pCache[index].data[way][3].b8._u64[0] = 0;
439     pCache[index].data[way][3].b8._u64[1] = 0;
440 william 31 break;
441     }
442 william 401 case 0x7: //IXIN (Instruction Cache Index Invalidate)
443     {
444     //Not Implemented as we do not have instruction cache
445     break;
446     }
447     case 0xC: //BFH (BTAC Flush)
448     {
449     //Not Implemented as we do not cache Branch Target Addresses.
450     break;
451     }
452     default:
453     CACHE_LOG("Cache mode %x not impemented", _Rt_);
454     break;
455 william 31 }
456     }
457     } // end namespace OpcodeImpl
458    
459 william 401 }}

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