/[pcsx2_0.9.7]/trunk/pcsx2/Cache.cpp
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Contents of /trunk/pcsx2/Cache.cpp

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Revision 31 - (show annotations) (download)
Tue Sep 7 03:24:11 2010 UTC (9 years, 5 months ago) by william
File size: 11750 byte(s)
committing r3113 initial commit again...
1 /* PCSX2 - PS2 Emulator for PCs
2 * Copyright (C) 2002-2010 PCSX2 Dev Team
3 *
4 * PCSX2 is free software: you can redistribute it and/or modify it under the terms
5 * of the GNU Lesser General Public License as published by the Free Software Found-
6 * ation, either version 3 of the License, or (at your option) any later version.
7 *
8 * PCSX2 is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
9 * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
10 * PURPOSE. See the GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License along with PCSX2.
13 * If not, see <http://www.gnu.org/licenses/>.
14 */
15
16
17 #include "PrecompiledHeader.h"
18 #include "Common.h"
19 #include "Cache.h"
20
21 _cacheS pCache[64];
22
23 namespace R5900{
24 namespace Interpreter
25 {
26 #ifdef PCSX2_CACHE_EMU_MEM
27
28 int getFreeCache(u32 mem, int mode, int * way) {
29 u8 * out;
30 u32 paddr;
31 u32 taddr[2];
32 u8 * t;
33 int number;
34 int i = (mem >> 6) & 0x3F;
35
36 paddr = getMemR(mem);
37 taddr[0] = getMemW(pCache[i].tag[0]);
38 taddr[1] = getMemW(pCache[i].tag[1]);
39
40 if (taddr[0] == paddr && (pCache[i].tag[0] & 0x20))
41 {
42 *way = 0;
43 return i;
44 }
45 else if(taddr[1] == paddr && (pCache[i].tag[1] & 0x20))
46 {
47 *way = 1;
48 return i;
49 }
50
51 number = ((pCache[i].tag[0]>>4) & 1) ^ ((pCache[i].tag[1]>>4) & 1);
52
53 if(pCache[i].tag[number] & 0x60) // Valid Dirty
54 {
55 t = (u8*)(taddr[number]);
56 out = (u8*)(t + (mem & 0xFC0));
57 ((u64*)out)[0] = ((u64*)pCache[i].data[number][0].b8._8)[0];
58 ((u64*)out)[1] = ((u64*)pCache[i].data[number][0].b8._8)[1];
59 ((u64*)out)[2] = ((u64*)pCache[i].data[number][1].b8._8)[0];
60 ((u64*)out)[3] = ((u64*)pCache[i].data[number][1].b8._8)[1];
61 ((u64*)out)[4] = ((u64*)pCache[i].data[number][2].b8._8)[0];
62 ((u64*)out)[5] = ((u64*)pCache[i].data[number][2].b8._8)[1];
63 ((u64*)out)[6] = ((u64*)pCache[i].data[number][3].b8._8)[0];
64 ((u64*)out)[7] = ((u64*)pCache[i].data[number][3].b8._8)[1];
65 }
66
67 if(mode == 1)
68 {
69 pCache[i].tag[number] |= 0x40; // Set Dirty Bit if mode == write
70 }
71
72 pCache[i].tag[number] &= ~(0xFFFFF000);
73 pCache[i].tag[number] |= ((mem>>12) & 0xFFFFF) << 12;
74
75
76 t = (u8 *)paddr;
77 out= (u8*)(t + (mem & 0xFC0));
78 ((u64*)pCache[i].data[number][0].b8._8)[0] = ((u64*)out)[0];
79 ((u64*)pCache[i].data[number][0].b8._8)[1] = ((u64*)out)[1];
80 ((u64*)pCache[i].data[number][1].b8._8)[0] = ((u64*)out)[2];
81 ((u64*)pCache[i].data[number][1].b8._8)[1] = ((u64*)out)[3];
82 ((u64*)pCache[i].data[number][2].b8._8)[0] = ((u64*)out)[4];
83 ((u64*)pCache[i].data[number][2].b8._8)[1] = ((u64*)out)[5];
84 ((u64*)pCache[i].data[number][3].b8._8)[0] = ((u64*)out)[6];
85 ((u64*)pCache[i].data[number][3].b8._8)[1] = ((u64*)out)[7];
86
87 if(pCache[i].tag[number] & 0x10)
88 pCache[i].tag[number] &= ~(0x10);
89 else
90 pCache[i].tag[number] |= 0x10;
91
92 pCache[i].tag[number] |= 0x20;
93 *way = number;
94 return i;
95 }
96
97 void writeCache8(u32 mem, u8 value) {
98 int i, number;
99
100 i = getFreeCache(mem,1,&number);
101 // CACHE_LOG("writeCache8 %8.8x adding to %d, way %d, value %x", mem, i,number,value);
102
103 pCache[i].data[number][(mem>>4) & 0x3].b8._8[(mem&0xf)] = value;
104 }
105
106 void writeCache16(u32 mem, u16 value) {
107 int i, number;
108
109 i = getFreeCache(mem,1,&number);
110 // CACHE_LOG("writeCache16 %8.8x adding to %d, way %d, value %x", mem, i,number,value);
111
112 *(u16*)(&pCache[i].data[number][(mem>>4) & 0x3].b8._8[(mem&0xf)]) = value;
113 }
114
115 void writeCache32(u32 mem, u32 value) {
116 int i, number;
117
118 i = getFreeCache(mem,1,&number);
119 // CACHE_LOG("writeCache32 %8.8x adding to %d, way %d, value %x", mem, i,number,value);
120 *(u32*)(&pCache[i].data[number][(mem>>4) & 0x3].b8._8[(mem&0xf)]) = value;
121 }
122
123 void writeCache64(u32 mem, u64 value) {
124 int i, number;
125
126 i = getFreeCache(mem,1,&number);
127 // CACHE_LOG("writeCache64 %8.8x adding to %d, way %d, value %x", mem, i,number,value);
128 *(u64*)(&pCache[i].data[number][(mem>>4) & 0x3].b8._8[(mem&0xf)]) = value;
129 }
130
131 void writeCache128(u32 mem, u64 *value) {
132 int i, number;
133
134 i = getFreeCache(mem,1,&number);
135 // CACHE_LOG("writeCache128 %8.8x adding to %d", mem, i);
136 ((u64*)pCache[i].data[number][(mem>>4) & 0x3].b8._8)[0] = value[0];
137 ((u64*)pCache[i].data[number][(mem>>4) & 0x3].b8._8)[1] = value[1];
138 }
139
140 u8 *readCache(u32 mem) {
141 int i, number;
142
143 i = getFreeCache(mem,0,&number);
144 // CACHE_LOG("readCache %8.8x from %d, way %d", mem, i,number);
145
146 return pCache[i].data[number][(mem>>4) & 0x3].b8._8;
147 }
148
149 namespace OpcodeImpl
150 {
151
152 extern int Dcache;
153 void CACHE() {
154 u32 addr;
155 //if(Dcache == 0) return;
156 addr = cpuRegs.GPR.r[_Rs_].UL[0] + _Imm_;
157 switch (_Rt_) {
158 case 0x1a:
159 {
160 int index = (addr >> 6) & 0x3F;
161 u32 paddr[2];
162 int way;
163 u32 taddr = getMemR(addr);
164 paddr[0] = getMemW(pCache[index].tag[0]);
165 paddr[1] = getMemW(pCache[index].tag[1]);
166
167 if(paddr[0] == taddr && (pCache[index].tag[0] & 0x20))
168 {
169 way = 0;
170 }
171 else if(paddr[1] == taddr && (pCache[index].tag[1] & 0x20))
172 {
173 way = 1;
174 }
175 else
176 {
177 return;
178 }
179
180 CACHE_LOG("CACHE DHIN addr %x, index %d, way %d, Flags %x",addr,index,way,pCache[index].tag[way] & 0x78);
181
182 pCache[index].tag[way] &= ~(0x6F);
183 ((u64*)pCache[index].data[way][0].b8._8)[0] = 0;
184 ((u64*)pCache[index].data[way][0].b8._8)[1] = 0;
185 ((u64*)pCache[index].data[way][1].b8._8)[0] = 0;
186 ((u64*)pCache[index].data[way][1].b8._8)[1] = 0;
187 ((u64*)pCache[index].data[way][2].b8._8)[0] = 0;
188 ((u64*)pCache[index].data[way][2].b8._8)[1] = 0;
189 ((u64*)pCache[index].data[way][3].b8._8)[0] = 0;
190 ((u64*)pCache[index].data[way][3].b8._8)[1] = 0;
191 break;
192 }
193 case 0x18:
194 {
195 u8 * out;
196 int index = (addr >> 6) & 0x3F;
197 u32 paddr[2];
198 int way;
199 u32 taddr = getMemW(addr);
200 paddr[0] = getMemW(pCache[index].tag[0]);
201 paddr[1] = getMemW(pCache[index].tag[1]);
202
203 if(paddr[0] == taddr && (pCache[index].tag[0] & 0x20))
204 {
205 way = 0;
206 }
207 else if(paddr[1] == taddr && (pCache[index].tag[1] & 0x20))
208 {
209 way = 1;
210 }
211 else
212 {
213 return;
214 }
215
216 CACHE_LOG("CACHE DHWBIN addr %x, index %d, way %d, Flags %x",addr,index,way,pCache[index].tag[way] & 0x78);
217
218 if(pCache[index].tag[way] & 0x60) // Valid Dirty
219 {
220 char * t = (char *)(taddr);//paddr[way]);
221 out = (u8*)(t + (addr & 0xFC0));
222 ((u64*)out)[0] = ((u64*)pCache[index].data[way][0].b8._8)[0];
223 ((u64*)out)[1] = ((u64*)pCache[index].data[way][0].b8._8)[1];
224 ((u64*)out)[2] = ((u64*)pCache[index].data[way][1].b8._8)[0];
225 ((u64*)out)[3] = ((u64*)pCache[index].data[way][1].b8._8)[1];
226 ((u64*)out)[4] = ((u64*)pCache[index].data[way][2].b8._8)[0];
227 ((u64*)out)[5] = ((u64*)pCache[index].data[way][2].b8._8)[1];
228 ((u64*)out)[6] = ((u64*)pCache[index].data[way][3].b8._8)[0];
229 ((u64*)out)[7] = ((u64*)pCache[index].data[way][3].b8._8)[1];
230 }
231
232 pCache[index].tag[way] &= ~(0x6F);
233 ((u64*)pCache[index].data[way][0].b8._8)[0] = 0;
234 ((u64*)pCache[index].data[way][0].b8._8)[1] = 0;
235 ((u64*)pCache[index].data[way][1].b8._8)[0] = 0;
236 ((u64*)pCache[index].data[way][1].b8._8)[1] = 0;
237 ((u64*)pCache[index].data[way][2].b8._8)[0] = 0;
238 ((u64*)pCache[index].data[way][2].b8._8)[1] = 0;
239 ((u64*)pCache[index].data[way][3].b8._8)[0] = 0;
240 ((u64*)pCache[index].data[way][3].b8._8)[1] = 0;
241
242 break;
243 }
244 case 0x1c:
245 {
246 u8 * out;
247 int index = (addr >> 6) & 0x3F;
248 u32 paddr[2];
249 int way;
250 u32 taddr = getMemW(addr);
251 paddr[0] = getMemW(pCache[index].tag[0]);
252 paddr[1] = getMemW(pCache[index].tag[1]);
253
254 if(paddr[0] == taddr && (pCache[index].tag[0] & 0x20))
255 {
256 way = 0;
257 }
258 else if(paddr[1] == taddr && (pCache[index].tag[1] & 0x20))
259 {
260 way = 1;
261 }
262 else
263 {
264 return;
265 }
266 CACHE_LOG("CACHE DHWOIN addr %x, index %d, way %d, Flags %x",addr,index,way,pCache[index].tag[way] & 0x78);
267
268 if(pCache[index].tag[way] & 0x60) // Valid Dirty
269 {
270 char * t = (char *)(taddr);
271 out = (u8*)(t + (addr & 0xFC0));
272 ((u64*)out)[0] = ((u64*)pCache[index].data[way][0].b8._8)[0];
273 ((u64*)out)[1] = ((u64*)pCache[index].data[way][0].b8._8)[1];
274 ((u64*)out)[2] = ((u64*)pCache[index].data[way][1].b8._8)[0];
275 ((u64*)out)[3] = ((u64*)pCache[index].data[way][1].b8._8)[1];
276 ((u64*)out)[4] = ((u64*)pCache[index].data[way][2].b8._8)[0];
277 ((u64*)out)[5] = ((u64*)pCache[index].data[way][2].b8._8)[1];
278 ((u64*)out)[6] = ((u64*)pCache[index].data[way][3].b8._8)[0];
279 ((u64*)out)[7] = ((u64*)pCache[index].data[way][3].b8._8)[1];
280 }
281
282 pCache[index].tag[way] &= ~(0x40);
283 break;
284 }
285 case 0x16:
286 {
287 int index = (addr >> 6) & 0x3F;
288 int way = addr & 0x1;
289
290 CACHE_LOG("CACHE DXIN addr %x, index %d, way %d, flag %x\n",addr,index,way,pCache[index].tag[way] & 0x78);
291
292 pCache[index].tag[way] &= ~(0x6F);
293
294 ((u64*)pCache[index].data[way][0].b8._8)[0] = 0;
295 ((u64*)pCache[index].data[way][0].b8._8)[1] = 0;
296 ((u64*)pCache[index].data[way][1].b8._8)[0] = 0;
297 ((u64*)pCache[index].data[way][1].b8._8)[1] = 0;
298 ((u64*)pCache[index].data[way][2].b8._8)[0] = 0;
299 ((u64*)pCache[index].data[way][2].b8._8)[1] = 0;
300 ((u64*)pCache[index].data[way][3].b8._8)[0] = 0;
301 ((u64*)pCache[index].data[way][3].b8._8)[1] = 0;
302 break;
303 }
304 case 0x11:
305 {
306 int index = (addr >> 6) & 0x3F;
307 int way = addr & 0x1;
308 u8 * out = pCache[index].data[way][(addr>>4) & 0x3].b8._8;
309 cpuRegs.CP0.r[28] = *(u32 *)(out+(addr&0xf));
310
311 CACHE_LOG("CACHE DXLDT addr %x, index %d, way %d, DATA %x",addr,index,way,cpuRegs.CP0.r[28]);
312
313 break;
314 }
315 case 0x10:
316 {
317 int index = (addr >> 6) & 0x3F;
318 int way = addr & 0x1;
319
320 cpuRegs.CP0.r[28] = 0;
321 cpuRegs.CP0.r[28] = pCache[index].tag[way];
322
323 CACHE_LOG("CACHE DXLTG addr %x, index %d, way %d, DATA %x",addr,index,way,cpuRegs.CP0.r[28]);
324
325 break;
326 }
327 case 0x13:
328 {
329 int index = (addr >> 6) & 0x3F;
330 int way = addr & 0x1;
331 //u8 * out = pCache[index].data[way][(addr>>4) & 0x3].b8._8;
332 *(u32*)(&pCache[index].data[way][(addr>>4) & 0x3].b8._8[(addr&0xf)]) = cpuRegs.CP0.r[28];
333
334 CACHE_LOG("CACHE DXSDT addr %x, index %d, way %d, DATA %x",addr,index,way,cpuRegs.CP0.r[28]);
335
336 break;
337 }
338 case 0x12:
339 {
340 int index = (addr >> 6) & 0x3F;
341 int way = addr & 0x1;
342 pCache[index].tag[way] = cpuRegs.CP0.r[28];
343
344 CACHE_LOG("CACHE DXSTG addr %x, index %d, way %d, DATA %x",addr,index,way,cpuRegs.CP0.r[28] & 0x6F);
345
346 break;
347 }
348 case 0x14:
349 {
350
351 u8 * out;
352 int index = (addr >> 6) & 0x3F;
353 int way = addr & 0x1;
354
355
356 CACHE_LOG("CACHE DXWBIN addr %x, index %d, way %d, Flags %x",addr,index,way,pCache[index].tag[way] & 0x78);
357
358 if(pCache[index].tag[way] & 0x60) // Dirty
359 {
360 u32 paddr = getMemW(pCache[index].tag[way]);
361 char * t = (char *)(paddr);
362 out = (u8*)(t + (addr & 0xFC0));
363 ((u64*)out)[0] = ((u64*)pCache[index].data[way][0].b8._8)[0];
364 ((u64*)out)[1] = ((u64*)pCache[index].data[way][0].b8._8)[1];
365 ((u64*)out)[2] = ((u64*)pCache[index].data[way][1].b8._8)[0];
366 ((u64*)out)[3] = ((u64*)pCache[index].data[way][1].b8._8)[1];
367 ((u64*)out)[4] = ((u64*)pCache[index].data[way][2].b8._8)[0];
368 ((u64*)out)[5] = ((u64*)pCache[index].data[way][2].b8._8)[1];
369 ((u64*)out)[6] = ((u64*)pCache[index].data[way][3].b8._8)[0];
370 ((u64*)out)[7] = ((u64*)pCache[index].data[way][3].b8._8)[1];
371 }
372
373 pCache[index].tag[way] &= ~(0x6F);
374 ((u64*)pCache[index].data[way][0].b8._8)[0] = 0;
375 ((u64*)pCache[index].data[way][0].b8._8)[1] = 0;
376 ((u64*)pCache[index].data[way][1].b8._8)[0] = 0;
377 ((u64*)pCache[index].data[way][1].b8._8)[1] = 0;
378 ((u64*)pCache[index].data[way][2].b8._8)[0] = 0;
379 ((u64*)pCache[index].data[way][2].b8._8)[1] = 0;
380 ((u64*)pCache[index].data[way][3].b8._8)[0] = 0;
381 ((u64*)pCache[index].data[way][3].b8._8)[1] = 0;
382 break;
383 }
384 }
385 }
386 } // end namespace OpcodeImpl
387 #else
388
389 namespace OpcodeImpl
390 {
391
392 void CACHE() {
393 }
394 }
395
396 #endif
397
398 }}

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