/[pcsx2_0.9.7]/trunk/common/include/x86emitter/tools.h
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Contents of /trunk/common/include/x86emitter/tools.h

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Revision 62 - (show annotations) (download)
Tue Sep 7 11:08:22 2010 UTC (9 years, 4 months ago) by william
File MIME type: text/plain
File size: 5680 byte(s)
Auto Commited Import of: pcsx2-0.9.7-r3738-debug in ./trunk
1 /* PCSX2 - PS2 Emulator for PCs
2 * Copyright (C) 2002-2010 PCSX2 Dev Team
3 *
4 * PCSX2 is free software: you can redistribute it and/or modify it under the terms
5 * of the GNU Lesser General Public License as published by the Free Software Found-
6 * ation, either version 3 of the License, or (at your option) any later version.
7 *
8 * PCSX2 is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
9 * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
10 * PURPOSE. See the GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License along with PCSX2.
13 * If not, see <http://www.gnu.org/licenses/>.
14 */
15
16 #pragma once
17
18 #include "x86emitter.h"
19
20 enum x86VendorType
21 {
22 x86Vendor_Intel=0,
23 x86Vendor_AMD,
24 x86Vendor_Unknown,
25 };
26
27 // --------------------------------------------------------------------------------------
28 // x86capabilities
29 // --------------------------------------------------------------------------------------
30 class x86capabilities
31 {
32 public:
33 bool isIdentified;
34 u32 LogicalCoresPerPhysicalCPU;
35 u32 PhysicalCoresPerPhysicalCPU;
36
37 public:
38 x86VendorType VendorID;
39
40 uint FamilyID; // Processor Family
41 uint Model; // Processor Model
42 uint TypeID; // Processor Type
43 uint StepID; // Stepping ID
44
45 u32 Flags; // Feature Flags
46 u32 Flags2; // More Feature Flags
47 u32 EFlags; // Extended Feature Flags
48 u32 EFlags2; // Extended Feature Flags pg2
49
50 char VendorName[16]; // Vendor/Creator ID
51 char FamilyName[50]; // the original cpu name
52
53 // ----------------------------------------------------------------------------
54 // x86 CPU Capabilities Section (all boolean flags!)
55 // ----------------------------------------------------------------------------
56
57 u32 hasFloatingPointUnit :1;
58 u32 hasVirtual8086ModeEnhancements :1;
59 u32 hasDebuggingExtensions :1;
60 u32 hasPageSizeExtensions :1;
61 u32 hasTimeStampCounter :1;
62 u32 hasModelSpecificRegisters :1;
63 u32 hasPhysicalAddressExtension :1;
64 u32 hasCOMPXCHG8BInstruction :1;
65 u32 hasAdvancedProgrammableInterruptController :1;
66 u32 hasSEPFastSystemCall :1;
67 u32 hasMemoryTypeRangeRegisters :1;
68 u32 hasPTEGlobalFlag :1;
69 u32 hasMachineCheckArchitecture :1;
70 u32 hasConditionalMoveAndCompareInstructions :1;
71 u32 hasFGPageAttributeTable :1;
72 u32 has36bitPageSizeExtension :1;
73 u32 hasProcessorSerialNumber :1;
74 u32 hasCFLUSHInstruction :1;
75 u32 hasDebugStore :1;
76 u32 hasACPIThermalMonitorAndClockControl :1;
77 u32 hasMultimediaExtensions :1;
78 u32 hasFastStreamingSIMDExtensionsSaveRestore :1;
79 u32 hasStreamingSIMDExtensions :1;
80 u32 hasStreamingSIMD2Extensions :1;
81 u32 hasSelfSnoop :1;
82
83 // is TRUE for both multi-core and Hyperthreaded CPUs.
84 u32 hasMultiThreading :1;
85
86 u32 hasThermalMonitor :1;
87 u32 hasIntel64BitArchitecture :1;
88 u32 hasStreamingSIMD3Extensions :1;
89 u32 hasSupplementalStreamingSIMD3Extensions :1;
90 u32 hasStreamingSIMD4Extensions :1;
91 u32 hasStreamingSIMD4Extensions2 :1;
92
93 // AMD-specific CPU Features
94 u32 hasMultimediaExtensionsExt :1;
95 u32 hasAMD64BitArchitecture :1;
96 u32 has3DNOWInstructionExtensionsExt :1;
97 u32 has3DNOWInstructionExtensions :1;
98 u32 hasStreamingSIMD4ExtensionsA :1;
99
100 // Core Counts!
101 u32 PhysicalCores;
102 u32 LogicalCores;
103
104 public:
105 x86capabilities()
106 {
107 isIdentified = false;
108 VendorID = x86Vendor_Unknown;
109 LogicalCoresPerPhysicalCPU = 1;
110 PhysicalCoresPerPhysicalCPU = 1;
111 }
112
113 void Identify();
114 void CountCores();
115 wxString GetTypeName() const;
116
117 u32 CalculateMHz() const;
118
119 void SIMD_ExceptionTest();
120 void SIMD_EstablishMXCSRmask();
121
122 protected:
123 s64 _CPUSpeedHz( u64 time ) const;
124 void CountLogicalCores();
125 };
126
127 enum SSE_RoundMode
128 {
129 SSE_RoundMode_FIRST = 0,
130 SSEround_Nearest = 0,
131 SSEround_NegInf,
132 SSEround_PosInf,
133 SSEround_Chop,
134 SSE_RoundMode_COUNT
135 };
136
137 ImplementEnumOperators( SSE_RoundMode );
138
139 // --------------------------------------------------------------------------------------
140 // SSE_MXCSR - Control/Status Register (bitfield)
141 // --------------------------------------------------------------------------------------
142 // Bits 0-5 are exception flags; used only if SSE exceptions have been enabled.
143 // Bits in this field are "sticky" and, once an exception has occured, must be manually
144 // cleared using LDMXCSR or FXRSTOR.
145 //
146 // Bits 7-12 are the masks for disabling the exceptions in bits 0-5. Cleared bits allow
147 // exceptions, set bits mask exceptions from being raised.
148 //
149 union SSE_MXCSR
150 {
151 u32 bitmask;
152 struct
153 {
154 u32
155 InvalidOpFlag :1,
156 DenormalFlag :1,
157 DivideByZeroFlag :1,
158 OverflowFlag :1,
159 UnderflowFlag :1,
160 PrecisionFlag :1,
161
162 // This bit is supported only on SSE2 or better CPUs. Setting it to 1 on
163 // SSE1 cpus will result in an invalid instruction exception when executing
164 // LDMXSCR.
165 DenormalsAreZero :1,
166
167 InvalidOpMask :1,
168 DenormalMask :1,
169 DivideByZeroMask :1,
170 OverflowMask :1,
171 UnderflowMask :1,
172 PrecisionMask :1,
173
174 RoundingControl :2,
175 FlushToZero :1;
176 };
177
178 SSE_RoundMode GetRoundMode() const;
179 SSE_MXCSR& SetRoundMode( SSE_RoundMode mode );
180 SSE_MXCSR& ClearExceptionFlags();
181 SSE_MXCSR& EnableExceptions();
182 SSE_MXCSR& DisableExceptions();
183
184 SSE_MXCSR& ApplyReserveMask();
185
186 bool operator ==( const SSE_MXCSR& right ) const
187 {
188 return bitmask == right.bitmask;
189 }
190
191 bool operator !=( const SSE_MXCSR& right ) const
192 {
193 return bitmask != right.bitmask;
194 }
195
196 operator x86Emitter::xIndirect32() const;
197 };
198
199 extern SSE_MXCSR MXCSR_Mask;
200
201
202 extern __aligned16 x86capabilities x86caps;
203

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