/[pcsx2_0.9.7]/trunk/common/include/x86emitter/tools.h
ViewVC logotype

Annotation of /trunk/common/include/x86emitter/tools.h

Parent Directory Parent Directory | Revision Log Revision Log


Revision 401 - (hide annotations) (download)
Fri Feb 25 17:31:09 2011 UTC (9 years, 5 months ago) by william
File MIME type: text/plain
File size: 5594 byte(s)
Auto Commited Import of: pcsx2-0.9.7-DEBUG (upstream: v0.9.7.4358 local: v0.9.7.313-latest) in ./trunk
1 william 31 /* PCSX2 - PS2 Emulator for PCs
2     * Copyright (C) 2002-2010 PCSX2 Dev Team
3     *
4     * PCSX2 is free software: you can redistribute it and/or modify it under the terms
5     * of the GNU Lesser General Public License as published by the Free Software Found-
6     * ation, either version 3 of the License, or (at your option) any later version.
7     *
8     * PCSX2 is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
9     * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
10     * PURPOSE. See the GNU General Public License for more details.
11     *
12     * You should have received a copy of the GNU General Public License along with PCSX2.
13     * If not, see <http://www.gnu.org/licenses/>.
14     */
15    
16     #pragma once
17    
18     #include "x86emitter.h"
19    
20 william 62 enum x86VendorType
21     {
22     x86Vendor_Intel=0,
23     x86Vendor_AMD,
24     x86Vendor_Unknown,
25     };
26 william 31
27     // --------------------------------------------------------------------------------------
28 william 62 // x86capabilities
29 william 31 // --------------------------------------------------------------------------------------
30 william 62 class x86capabilities
31 william 31 {
32 william 62 public:
33     bool isIdentified;
34    
35     public:
36     x86VendorType VendorID;
37    
38     uint FamilyID; // Processor Family
39     uint Model; // Processor Model
40     uint TypeID; // Processor Type
41     uint StepID; // Stepping ID
42    
43 william 31 u32 Flags; // Feature Flags
44     u32 Flags2; // More Feature Flags
45     u32 EFlags; // Extended Feature Flags
46     u32 EFlags2; // Extended Feature Flags pg2
47    
48     char VendorName[16]; // Vendor/Creator ID
49     char FamilyName[50]; // the original cpu name
50    
51     // ----------------------------------------------------------------------------
52     // x86 CPU Capabilities Section (all boolean flags!)
53     // ----------------------------------------------------------------------------
54    
55 william 62 u32 hasFloatingPointUnit :1;
56     u32 hasVirtual8086ModeEnhancements :1;
57     u32 hasDebuggingExtensions :1;
58     u32 hasPageSizeExtensions :1;
59     u32 hasTimeStampCounter :1;
60     u32 hasModelSpecificRegisters :1;
61     u32 hasPhysicalAddressExtension :1;
62     u32 hasCOMPXCHG8BInstruction :1;
63     u32 hasAdvancedProgrammableInterruptController :1;
64     u32 hasSEPFastSystemCall :1;
65     u32 hasMemoryTypeRangeRegisters :1;
66     u32 hasPTEGlobalFlag :1;
67     u32 hasMachineCheckArchitecture :1;
68     u32 hasConditionalMoveAndCompareInstructions :1;
69     u32 hasFGPageAttributeTable :1;
70     u32 has36bitPageSizeExtension :1;
71     u32 hasProcessorSerialNumber :1;
72     u32 hasCFLUSHInstruction :1;
73     u32 hasDebugStore :1;
74     u32 hasACPIThermalMonitorAndClockControl :1;
75     u32 hasMultimediaExtensions :1;
76     u32 hasFastStreamingSIMDExtensionsSaveRestore :1;
77     u32 hasStreamingSIMDExtensions :1;
78     u32 hasStreamingSIMD2Extensions :1;
79     u32 hasSelfSnoop :1;
80 william 31
81 william 62 // is TRUE for both multi-core and Hyperthreaded CPUs.
82     u32 hasMultiThreading :1;
83    
84     u32 hasThermalMonitor :1;
85     u32 hasIntel64BitArchitecture :1;
86     u32 hasStreamingSIMD3Extensions :1;
87     u32 hasSupplementalStreamingSIMD3Extensions :1;
88     u32 hasStreamingSIMD4Extensions :1;
89     u32 hasStreamingSIMD4Extensions2 :1;
90 william 401 u32 hasAVX :1;
91     u32 hasFMA :1;
92 william 62
93     // AMD-specific CPU Features
94     u32 hasMultimediaExtensionsExt :1;
95     u32 hasAMD64BitArchitecture :1;
96     u32 has3DNOWInstructionExtensionsExt :1;
97     u32 has3DNOWInstructionExtensions :1;
98     u32 hasStreamingSIMD4ExtensionsA :1;
99    
100     // Core Counts!
101     u32 PhysicalCores;
102     u32 LogicalCores;
103    
104     public:
105     x86capabilities()
106     {
107     isIdentified = false;
108     VendorID = x86Vendor_Unknown;
109     }
110    
111     void Identify();
112     void CountCores();
113     wxString GetTypeName() const;
114    
115     u32 CalculateMHz() const;
116    
117     void SIMD_ExceptionTest();
118     void SIMD_EstablishMXCSRmask();
119    
120     protected:
121     s64 _CPUSpeedHz( u64 time ) const;
122     void CountLogicalCores();
123 william 31 };
124    
125     enum SSE_RoundMode
126     {
127 william 62 SSE_RoundMode_FIRST = 0,
128 william 31 SSEround_Nearest = 0,
129     SSEround_NegInf,
130     SSEround_PosInf,
131     SSEround_Chop,
132 william 62 SSE_RoundMode_COUNT
133 william 31 };
134    
135 william 62 ImplementEnumOperators( SSE_RoundMode );
136    
137 william 31 // --------------------------------------------------------------------------------------
138     // SSE_MXCSR - Control/Status Register (bitfield)
139     // --------------------------------------------------------------------------------------
140     // Bits 0-5 are exception flags; used only if SSE exceptions have been enabled.
141     // Bits in this field are "sticky" and, once an exception has occured, must be manually
142     // cleared using LDMXCSR or FXRSTOR.
143     //
144     // Bits 7-12 are the masks for disabling the exceptions in bits 0-5. Cleared bits allow
145     // exceptions, set bits mask exceptions from being raised.
146     //
147     union SSE_MXCSR
148     {
149     u32 bitmask;
150     struct
151     {
152     u32
153     InvalidOpFlag :1,
154     DenormalFlag :1,
155     DivideByZeroFlag :1,
156     OverflowFlag :1,
157     UnderflowFlag :1,
158     PrecisionFlag :1,
159    
160     // This bit is supported only on SSE2 or better CPUs. Setting it to 1 on
161     // SSE1 cpus will result in an invalid instruction exception when executing
162     // LDMXSCR.
163     DenormalsAreZero :1,
164    
165     InvalidOpMask :1,
166     DenormalMask :1,
167     DivideByZeroMask :1,
168     OverflowMask :1,
169     UnderflowMask :1,
170     PrecisionMask :1,
171    
172     RoundingControl :2,
173     FlushToZero :1;
174     };
175    
176     SSE_RoundMode GetRoundMode() const;
177     SSE_MXCSR& SetRoundMode( SSE_RoundMode mode );
178     SSE_MXCSR& ClearExceptionFlags();
179     SSE_MXCSR& EnableExceptions();
180     SSE_MXCSR& DisableExceptions();
181    
182     SSE_MXCSR& ApplyReserveMask();
183    
184     bool operator ==( const SSE_MXCSR& right ) const
185     {
186     return bitmask == right.bitmask;
187     }
188    
189     bool operator !=( const SSE_MXCSR& right ) const
190     {
191     return bitmask != right.bitmask;
192     }
193    
194 william 62 operator x86Emitter::xIndirect32() const;
195 william 31 };
196    
197     extern SSE_MXCSR MXCSR_Mask;
198    
199    
200 william 62 extern __aligned16 x86capabilities x86caps;
201 william 31

  ViewVC Help
Powered by ViewVC 1.1.22