/[pcsx2_0.9.7]/trunk/common/include/x86emitter/tools.h
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Annotation of /trunk/common/include/x86emitter/tools.h

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Revision 31 - (hide annotations) (download)
Tue Sep 7 03:24:11 2010 UTC (9 years, 11 months ago) by william
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File size: 5966 byte(s)
committing r3113 initial commit again...
1 william 31 /* PCSX2 - PS2 Emulator for PCs
2     * Copyright (C) 2002-2010 PCSX2 Dev Team
3     *
4     * PCSX2 is free software: you can redistribute it and/or modify it under the terms
5     * of the GNU Lesser General Public License as published by the Free Software Found-
6     * ation, either version 3 of the License, or (at your option) any later version.
7     *
8     * PCSX2 is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
9     * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
10     * PURPOSE. See the GNU General Public License for more details.
11     *
12     * You should have received a copy of the GNU General Public License along with PCSX2.
13     * If not, see <http://www.gnu.org/licenses/>.
14     */
15    
16     #pragma once
17    
18     #include "x86emitter.h"
19    
20     // this is all that needs to be called and will fill up the below structs
21     extern void cpudetectInit();
22    
23     // Returns the number of available logical CPUs (cores plus hyperthreaded cpus)
24     extern void CountLogicalCores( int LogicalCoresPerPhysicalCPU, int PhysicalCoresPerPhysicalCPU );
25    
26     // --------------------------------------------------------------------------------------
27     // x86CPU_INFO
28     // --------------------------------------------------------------------------------------
29     struct x86CPU_INFO
30     {
31     u32 FamilyID; // Processor Family
32     u32 Model; // Processor Model
33     u32 TypeID; // Processor Type
34     u32 StepID; // Stepping ID
35     u32 Flags; // Feature Flags
36     u32 Flags2; // More Feature Flags
37     u32 EFlags; // Extended Feature Flags
38     u32 EFlags2; // Extended Feature Flags pg2
39    
40     u32 PhysicalCores;
41     u32 LogicalCores;
42    
43     char VendorName[16]; // Vendor/Creator ID
44     char TypeName[20]; // cpu type
45     char FamilyName[50]; // the original cpu name
46    
47     // Speed - speed of cpu in mhz
48     // This is a rough "real" measure of the cpu speed, taken at application startup.
49     // Not to be considered totally accurate: Power saving CPUs and SpeedStep can skew
50     // results considerably.
51     u32 Speed;
52    
53     // ----------------------------------------------------------------------------
54     // x86 CPU Capabilities Section (all boolean flags!)
55     // ----------------------------------------------------------------------------
56    
57     u32 hasFloatingPointUnit:1;
58     u32 hasVirtual8086ModeEnhancements:1;
59     u32 hasDebuggingExtensions:1;
60     u32 hasPageSizeExtensions:1;
61     u32 hasTimeStampCounter:1;
62     u32 hasModelSpecificRegisters:1;
63     u32 hasPhysicalAddressExtension:1;
64     u32 hasCOMPXCHG8BInstruction:1;
65     u32 hasAdvancedProgrammableInterruptController:1;
66     u32 hasSEPFastSystemCall:1;
67     u32 hasMemoryTypeRangeRegisters:1;
68     u32 hasPTEGlobalFlag:1;
69     u32 hasMachineCheckArchitecture:1;
70     u32 hasConditionalMoveAndCompareInstructions:1;
71     u32 hasFGPageAttributeTable:1;
72     u32 has36bitPageSizeExtension:1;
73     u32 hasProcessorSerialNumber:1;
74     u32 hasCFLUSHInstruction:1;
75     u32 hasDebugStore:1;
76     u32 hasACPIThermalMonitorAndClockControl:1;
77     u32 hasMultimediaExtensions:1;
78     u32 hasFastStreamingSIMDExtensionsSaveRestore:1;
79     u32 hasStreamingSIMDExtensions:1;
80     u32 hasStreamingSIMD2Extensions:1;
81     u32 hasSelfSnoop:1;
82     u32 hasMultiThreading:1; // is TRUE for both multi-core and Hyperthreaded CPUs.
83     u32 hasThermalMonitor:1;
84     u32 hasIntel64BitArchitecture:1;
85     u32 hasStreamingSIMD3Extensions:1;
86     u32 hasSupplementalStreamingSIMD3Extensions:1;
87     u32 hasStreamingSIMD4Extensions:1;
88     u32 hasStreamingSIMD4Extensions2:1;
89    
90     // AMD-specific CPU Features
91     u32 hasMultimediaExtensionsExt:1;
92     u32 hasAMD64BitArchitecture:1;
93     u32 has3DNOWInstructionExtensionsExt:1;
94     u32 has3DNOWInstructionExtensions:1;
95     u32 hasStreamingSIMD4ExtensionsA:1;
96     };
97    
98     enum SSE_RoundMode
99     {
100     SSEround_Nearest = 0,
101     SSEround_NegInf,
102     SSEround_PosInf,
103     SSEround_Chop,
104     };
105    
106     // --------------------------------------------------------------------------------------
107     // SSE_MXCSR - Control/Status Register (bitfield)
108     // --------------------------------------------------------------------------------------
109     // Bits 0-5 are exception flags; used only if SSE exceptions have been enabled.
110     // Bits in this field are "sticky" and, once an exception has occured, must be manually
111     // cleared using LDMXCSR or FXRSTOR.
112     //
113     // Bits 7-12 are the masks for disabling the exceptions in bits 0-5. Cleared bits allow
114     // exceptions, set bits mask exceptions from being raised.
115     //
116     union SSE_MXCSR
117     {
118     u32 bitmask;
119     struct
120     {
121     u32
122     InvalidOpFlag :1,
123     DenormalFlag :1,
124     DivideByZeroFlag :1,
125     OverflowFlag :1,
126     UnderflowFlag :1,
127     PrecisionFlag :1,
128    
129     // This bit is supported only on SSE2 or better CPUs. Setting it to 1 on
130     // SSE1 cpus will result in an invalid instruction exception when executing
131     // LDMXSCR.
132     DenormalsAreZero :1,
133    
134     InvalidOpMask :1,
135     DenormalMask :1,
136     DivideByZeroMask :1,
137     OverflowMask :1,
138     UnderflowMask :1,
139     PrecisionMask :1,
140    
141     RoundingControl :2,
142     FlushToZero :1;
143     };
144    
145     SSE_RoundMode GetRoundMode() const;
146     SSE_MXCSR& SetRoundMode( SSE_RoundMode mode );
147     SSE_MXCSR& ClearExceptionFlags();
148     SSE_MXCSR& EnableExceptions();
149     SSE_MXCSR& DisableExceptions();
150    
151     SSE_MXCSR& ApplyReserveMask();
152    
153     bool operator ==( const SSE_MXCSR& right ) const
154     {
155     return bitmask == right.bitmask;
156     }
157    
158     bool operator !=( const SSE_MXCSR& right ) const
159     {
160     return bitmask != right.bitmask;
161     }
162    
163     operator x86Emitter::ModSib32() const;
164     };
165    
166     extern SSE_MXCSR MXCSR_Mask;
167    
168     //////////////////////////////////////////////////////////////////////////////////////////
169    
170    
171     extern __aligned16 x86CPU_INFO x86caps;
172    
173     extern bool g_EEFreezeRegs;
174    
175     // when using mmx/xmm regs, use these functions.
176    
177     namespace MMXRegisters
178     {
179     extern void Freeze();
180     extern void Thaw();
181     extern bool Saved();
182     extern __aligned16 u64 data[8];
183     };
184    
185     namespace XMMRegisters
186     {
187     extern void Freeze();
188     extern void Thaw();
189     extern bool Saved();
190     extern __aligned16 u64 data[2*iREGCNT_XMM];
191     };
192    
193     namespace Registers
194     {
195     extern void Freeze();
196     extern void Thaw();
197     extern bool Saved();
198     };
199    

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