/[pcsx2_0.9.7]/trunk/common/include/x86emitter/implement/simd_shufflepack.h
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Contents of /trunk/common/include/x86emitter/implement/simd_shufflepack.h

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Revision 31 - (show annotations) (download)
Tue Sep 7 03:24:11 2010 UTC (9 years, 10 months ago) by william
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committing r3113 initial commit again...
1 /* PCSX2 - PS2 Emulator for PCs
2 * Copyright (C) 2002-2010 PCSX2 Dev Team
3 *
4 * PCSX2 is free software: you can redistribute it and/or modify it under the terms
5 * of the GNU Lesser General Public License as published by the Free Software Found-
6 * ation, either version 3 of the License, or (at your option) any later version.
7 *
8 * PCSX2 is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
9 * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
10 * PURPOSE. See the GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License along with PCSX2.
13 * If not, see <http://www.gnu.org/licenses/>.
14 */
15
16 #pragma once
17
18 namespace x86Emitter {
19
20 // --------------------------------------------------------------------------------------
21 // xImplSimd_Shuffle
22 // --------------------------------------------------------------------------------------
23 struct xImplSimd_Shuffle
24 {
25 inline void _selector_assertion_check( u8 selector ) const;
26
27 void PS( const xRegisterSSE& to, const xRegisterSSE& from, u8 selector ) const;
28 void PS( const xRegisterSSE& to, const ModSibBase& from, u8 selector ) const;
29
30 void PD( const xRegisterSSE& to, const xRegisterSSE& from, u8 selector ) const;
31 void PD( const xRegisterSSE& to, const ModSibBase& from, u8 selector ) const;
32 };
33
34 // --------------------------------------------------------------------------------------
35 // xImplSimd_PShuffle
36 // --------------------------------------------------------------------------------------
37 struct xImplSimd_PShuffle
38 {
39 // Copies words from src and inserts them into dest at word locations selected with
40 // the order operand (8 bit immediate).
41 const xImplSimd_DestRegImmMMX W;
42
43 // Copies doublewords from src and inserts them into dest at dword locations selected
44 // with the order operand (8 bit immediate).
45 const xImplSimd_DestRegImmSSE D;
46
47 // Copies words from the low quadword of src and inserts them into the low quadword
48 // of dest at word locations selected with the order operand (8 bit immediate).
49 // The high quadword of src is copied to the high quadword of dest.
50 const xImplSimd_DestRegImmSSE LW;
51
52 // Copies words from the high quadword of src and inserts them into the high quadword
53 // of dest at word locations selected with the order operand (8 bit immediate).
54 // The low quadword of src is copied to the low quadword of dest.
55 const xImplSimd_DestRegImmSSE HW;
56
57 // [sSSE-3] Performs in-place shuffles of bytes in dest according to the shuffle
58 // control mask in src. If the most significant bit (bit[7]) of each byte of the
59 // shuffle control mask is set, then constant zero is written in the result byte.
60 // Each byte in the shuffle control mask forms an index to permute the corresponding
61 // byte in dest. The value of each index is the least significant 4 bits (128-bit
62 // operation) or 3 bits (64-bit operation) of the shuffle control byte.
63 //
64 // Operands can be MMX or XMM registers.
65 const xImplSimd_DestRegEither B;
66 };
67
68 // --------------------------------------------------------------------------------------
69 // SimdImpl_PUnpack
70 // --------------------------------------------------------------------------------------
71 struct SimdImpl_PUnpack
72 {
73 // Unpack and interleave low-order bytes from src and dest into dest.
74 const xImplSimd_DestRegEither LBW;
75 // Unpack and interleave low-order words from src and dest into dest.
76 const xImplSimd_DestRegEither LWD;
77 // Unpack and interleave low-order doublewords from src and dest into dest.
78 const xImplSimd_DestRegEither LDQ;
79 // Unpack and interleave low-order quadwords from src and dest into dest.
80 const xImplSimd_DestRegSSE LQDQ;
81
82 // Unpack and interleave high-order bytes from src and dest into dest.
83 const xImplSimd_DestRegEither HBW;
84 // Unpack and interleave high-order words from src and dest into dest.
85 const xImplSimd_DestRegEither HWD;
86 // Unpack and interleave high-order doublewords from src and dest into dest.
87 const xImplSimd_DestRegEither HDQ;
88 // Unpack and interleave high-order quadwords from src and dest into dest.
89 const xImplSimd_DestRegSSE HQDQ;
90 };
91
92 // --------------------------------------------------------------------------------------
93 // SimdImpl_Pack
94 // --------------------------------------------------------------------------------------
95 // Pack with Signed or Unsigned Saturation
96 //
97 struct SimdImpl_Pack
98 {
99 // Converts packed signed word integers from src and dest into packed signed
100 // byte integers in dest, using signed saturation.
101 const xImplSimd_DestRegEither SSWB;
102
103 // Converts packed signed dword integers from src and dest into packed signed
104 // word integers in dest, using signed saturation.
105 const xImplSimd_DestRegEither SSDW;
106
107 // Converts packed unsigned word integers from src and dest into packed unsigned
108 // byte integers in dest, using unsigned saturation.
109 const xImplSimd_DestRegEither USWB;
110
111 // [SSE-4.1] Converts packed unsigned dword integers from src and dest into packed
112 // unsigned word integers in dest, using signed saturation.
113 const xImplSimd_DestRegSSE USDW;
114 };
115
116 // --------------------------------------------------------------------------------------
117 // SimdImpl_Unpack
118 // --------------------------------------------------------------------------------------
119 struct xImplSimd_Unpack
120 {
121 // Unpacks the high doubleword [single-precision] values from src and dest into
122 // dest, such that the result of dest looks like this:
123 // dest[0] <- dest[2]
124 // dest[1] <- src[2]
125 // dest[2] <- dest[3]
126 // dest[3] <- src[3]
127 //
128 const xImplSimd_DestRegSSE HPS;
129
130 // Unpacks the high quadword [double-precision] values from src and dest into
131 // dest, such that the result of dest looks like this:
132 // dest.lo <- dest.hi
133 // dest.hi <- src.hi
134 //
135 const xImplSimd_DestRegSSE HPD;
136
137 // Unpacks the low doubleword [single-precision] values from src and dest into
138 // dest, such that the result of dest looks like this:
139 // dest[3] <- src[1]
140 // dest[2] <- dest[1]
141 // dest[1] <- src[0]
142 // dest[0] <- dest[0]
143 //
144 const xImplSimd_DestRegSSE LPS;
145
146 // Unpacks the low quadword [double-precision] values from src and dest into
147 // dest, effectively moving the low portion of src into the upper portion of dest.
148 // The result of dest is loaded as such:
149 // dest.hi <- src.lo
150 // dest.lo <- dest.lo [remains unchanged!]
151 //
152 const xImplSimd_DestRegSSE LPD;
153 };
154
155
156 struct xImplSimd_InsertExtractHelper
157 {
158 u16 Opcode;
159
160 // [SSE-4.1] Allowed with SSE registers only (MMX regs are invalid)
161 void operator()( const xRegisterSSE& to, const xRegister32& from, u8 imm8 ) const;
162
163 // [SSE-4.1] Allowed with SSE registers only (MMX regs are invalid)
164 void operator()( const xRegisterSSE& to, const ModSibBase& from, u8 imm8 ) const;
165 };
166
167 // --------------------------------------------------------------------------------------
168 // SimdImpl_PInsert
169 // --------------------------------------------------------------------------------------
170 // PINSRW/B/D [all but Word form are SSE4.1 only!]
171 //
172 struct xImplSimd_PInsert
173 {
174 void W( const xRegisterSSE& to, const xRegister32& from, u8 imm8 ) const;
175 void W( const xRegisterSSE& to, const ModSibBase& from, u8 imm8 ) const;
176
177 void W( const xRegisterMMX& to, const xRegister32& from, u8 imm8 ) const;
178 void W( const xRegisterMMX& to, const ModSibBase& from, u8 imm8 ) const;
179
180 // [SSE-4.1] Allowed with SSE registers only (MMX regs are invalid)
181 xImplSimd_InsertExtractHelper B;
182
183 // [SSE-4.1] Allowed with SSE registers only (MMX regs are invalid)
184 xImplSimd_InsertExtractHelper D;
185 };
186
187
188 //////////////////////////////////////////////////////////////////////////////////////////
189 // PEXTRW/B/D [all but Word form are SSE4.1 only!]
190 //
191 // Note: Word form's indirect memory form is only available in SSE4.1.
192 //
193 struct SimdImpl_PExtract
194 {
195 // Copies the word element specified by imm8 from src to dest. The upper bits
196 // of dest are zero-extended (cleared). This can be used to extract any single packed
197 // word value from src into an x86 32 bit register.
198 //
199 // [SSE-4.1] Note: Indirect memory forms of this instruction are an SSE-4.1 extension!
200 //
201 void W( const xRegister32& to, const xRegisterSSE& from, u8 imm8 ) const;
202 void W( const xRegister32& to, const xRegisterMMX& from, u8 imm8 ) const;
203 void W( const ModSibBase& dest, const xRegisterSSE& from, u8 imm8 ) const;
204
205 // [SSE-4.1] Copies the byte element specified by imm8 from src to dest. The upper bits
206 // of dest are zero-extended (cleared). This can be used to extract any single packed
207 // byte value from src into an x86 32 bit register.
208 const xImplSimd_InsertExtractHelper B;
209
210 // [SSE-4.1] Copies the dword element specified by imm8 from src to dest. This can be
211 // used to extract any single packed dword value from src into an x86 32 bit register.
212 const xImplSimd_InsertExtractHelper D;
213 };
214
215 }

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