/[pcsx2_0.9.7]/trunk/common/include/x86emitter/implement/simd_moremovs.h
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Contents of /trunk/common/include/x86emitter/implement/simd_moremovs.h

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Revision 62 - (show annotations) (download)
Tue Sep 7 11:08:22 2010 UTC (10 years, 1 month ago) by william
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Auto Commited Import of: pcsx2-0.9.7-r3738-debug in ./trunk
1 /* PCSX2 - PS2 Emulator for PCs
2 * Copyright (C) 2002-2010 PCSX2 Dev Team
3 *
4 * PCSX2 is free software: you can redistribute it and/or modify it under the terms
5 * of the GNU Lesser General Public License as published by the Free Software Found-
6 * ation, either version 3 of the License, or (at your option) any later version.
7 *
8 * PCSX2 is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
9 * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
10 * PURPOSE. See the GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License along with PCSX2.
13 * If not, see <http://www.gnu.org/licenses/>.
14 */
15
16 #pragma once
17
18 namespace x86Emitter {
19
20 // --------------------------------------------------------------------------------------
21 // xImplSimd_MovHL
22 // --------------------------------------------------------------------------------------
23 // Moves to/from high/low portions of an xmm register.
24 // These instructions cannot be used in reg/reg form.
25 //
26 struct xImplSimd_MovHL
27 {
28 u16 Opcode;
29
30 void PS( const xRegisterSSE& to, const xIndirectVoid& from ) const;
31 void PS( const xIndirectVoid& to, const xRegisterSSE& from ) const;
32
33 void PD( const xRegisterSSE& to, const xIndirectVoid& from ) const;
34 void PD( const xIndirectVoid& to, const xRegisterSSE& from ) const;
35 };
36
37 // --------------------------------------------------------------------------------------
38 // xImplSimd_MovHL_RtoR
39 // --------------------------------------------------------------------------------------
40 // RegtoReg forms of MOVHL/MOVLH -- these are the same opcodes as MOVH/MOVL but
41 // do something kinda different! Fun!
42 //
43 struct xImplSimd_MovHL_RtoR
44 {
45 u16 Opcode;
46
47 void PS( const xRegisterSSE& to, const xRegisterSSE& from ) const;
48 void PD( const xRegisterSSE& to, const xRegisterSSE& from ) const;
49 };
50
51 // --------------------------------------------------------------------------------------
52 // xImplSimd_MoveSSE
53 // --------------------------------------------------------------------------------------
54 // Legends in their own right: MOVAPS / MOVAPD / MOVUPS / MOVUPD
55 //
56 // All implementations of Unaligned Movs will, when possible, use aligned movs instead.
57 // This happens when using Mem,Reg or Reg,Mem forms where the address is simple displacement
58 // which can be checked for alignment at runtime.
59 //
60 struct xImplSimd_MoveSSE
61 {
62 u8 Prefix;
63 bool isAligned;
64
65 void operator()( const xRegisterSSE& to, const xRegisterSSE& from ) const;
66 void operator()( const xRegisterSSE& to, const xIndirectVoid& from ) const;
67 void operator()( const xIndirectVoid& to, const xRegisterSSE& from ) const;
68 };
69
70 // --------------------------------------------------------------------------------------
71 // xImplSimd_MoveDQ
72 // --------------------------------------------------------------------------------------
73 // Implementations for MOVDQA / MOVDQU
74 //
75 // All implementations of Unaligned Movs will, when possible, use aligned movs instead.
76 // This happens when using Mem,Reg or Reg,Mem forms where the address is simple displacement
77 // which can be checked for alignment at runtime.
78
79 struct xImplSimd_MoveDQ
80 {
81 u8 Prefix;
82 bool isAligned;
83
84 void operator()( const xRegisterSSE& to, const xRegisterSSE& from ) const;
85 void operator()( const xRegisterSSE& to, const xIndirectVoid& from ) const;
86 void operator()( const xIndirectVoid& to, const xRegisterSSE& from ) const;
87 };
88
89 // --------------------------------------------------------------------------------------
90 // xImplSimd_Blend
91 // --------------------------------------------------------------------------------------
92 // Blend - Conditional copying of values in src into dest.
93 //
94 struct xImplSimd_Blend
95 {
96 // [SSE-4.1] Conditionally copies dword values from src to dest, depending on the
97 // mask bits in the immediate operand (bits [3:0]). Each mask bit corresponds to a
98 // dword element in a 128-bit operand.
99 //
100 // If a mask bit is 1, then the corresponding dword in the source operand is copied
101 // to dest, else the dword element in dest is left unchanged.
102 //
103 xImplSimd_DestRegImmSSE PS;
104
105 // [SSE-4.1] Conditionally copies quadword values from src to dest, depending on the
106 // mask bits in the immediate operand (bits [1:0]). Each mask bit corresponds to a
107 // quadword element in a 128-bit operand.
108 //
109 // If a mask bit is 1, then the corresponding dword in the source operand is copied
110 // to dest, else the dword element in dest is left unchanged.
111 //
112 xImplSimd_DestRegImmSSE PD;
113
114 // [SSE-4.1] Conditionally copies dword values from src to dest, depending on the
115 // mask (bits [3:0]) in XMM0 (yes, the fixed register). Each mask bit corresponds
116 // to a dword element in the 128-bit operand.
117 //
118 // If a mask bit is 1, then the corresponding dword in the source operand is copied
119 // to dest, else the dword element in dest is left unchanged.
120 //
121 xImplSimd_DestRegSSE VPS;
122
123 // [SSE-4.1] Conditionally copies quadword values from src to dest, depending on the
124 // mask (bits [1:0]) in XMM0 (yes, the fixed register). Each mask bit corresponds
125 // to a quadword element in the 128-bit operand.
126 //
127 // If a mask bit is 1, then the corresponding dword in the source operand is copied
128 // to dest, else the dword element in dest is left unchanged.
129 //
130 xImplSimd_DestRegSSE VPD;
131 };
132
133 // --------------------------------------------------------------------------------------
134 // xImplSimd_PMove
135 // --------------------------------------------------------------------------------------
136 // Packed Move with Sign or Zero extension.
137 //
138 struct xImplSimd_PMove
139 {
140 u16 OpcodeBase;
141
142 // [SSE-4.1] Zero/Sign-extend the low byte values in src into word integers
143 // and store them in dest.
144 void BW( const xRegisterSSE& to, const xRegisterSSE& from ) const;
145 void BW( const xRegisterSSE& to, const xIndirect64& from ) const;
146
147 // [SSE-4.1] Zero/Sign-extend the low byte values in src into dword integers
148 // and store them in dest.
149 void BD( const xRegisterSSE& to, const xRegisterSSE& from ) const;
150 void BD( const xRegisterSSE& to, const xIndirect32& from ) const;
151
152 // [SSE-4.1] Zero/Sign-extend the low byte values in src into qword integers
153 // and store them in dest.
154 void BQ( const xRegisterSSE& to, const xRegisterSSE& from ) const;
155 void BQ( const xRegisterSSE& to, const xIndirect16& from ) const;
156
157 // [SSE-4.1] Zero/Sign-extend the low word values in src into dword integers
158 // and store them in dest.
159 void WD( const xRegisterSSE& to, const xRegisterSSE& from ) const;
160 void WD( const xRegisterSSE& to, const xIndirect64& from ) const;
161
162 // [SSE-4.1] Zero/Sign-extend the low word values in src into qword integers
163 // and store them in dest.
164 void WQ( const xRegisterSSE& to, const xRegisterSSE& from ) const;
165 void WQ( const xRegisterSSE& to, const xIndirect32& from ) const;
166
167 // [SSE-4.1] Zero/Sign-extend the low dword values in src into qword integers
168 // and store them in dest.
169 void DQ( const xRegisterSSE& to, const xRegisterSSE& from ) const;
170 void DQ( const xRegisterSSE& to, const xIndirect64& from ) const;
171 };
172
173 }
174

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