/[pcsx2_0.9.7]/branch/debug/0.X/0.9.X/0.9.7/ramdump-lateset/plugins/zzogl-pg/opengl/Regs.h
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Contents of /branch/debug/0.X/0.9.X/0.9.7/ramdump-lateset/plugins/zzogl-pg/opengl/Regs.h

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Revision 330 - (show annotations) (download)
Tue Dec 28 04:24:23 2010 UTC (9 years, 9 months ago) by william
File MIME type: text/plain
File size: 18442 byte(s)
merged upstream r4154-r4160
1 /* ZZ Open GL graphics plugin
2 * Copyright (c)2009-2010 zeydlitz@gmail.com, arcum42@gmail.com
3 * Based on Zerofrog's ZeroGS KOSMOS (c)2005-2008
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
18 */
19
20 #ifndef __GSREGS_H__
21 #define __GSREGS_H__
22
23
24 #ifdef USE_OLD_REGS
25
26 enum GIF_REG
27 {
28 GIF_REG_PRIM = 0x00,
29 GIF_REG_RGBA = 0x01,
30 GIF_REG_STQ = 0x02,
31 GIF_REG_UV = 0x03,
32 GIF_REG_XYZF2 = 0x04,
33 GIF_REG_XYZ2 = 0x05,
34 GIF_REG_TEX0_1 = 0x06,
35 GIF_REG_TEX0_2 = 0x07,
36 GIF_REG_CLAMP_1 = 0x08,
37 GIF_REG_CLAMP_2 = 0x09,
38 GIF_REG_FOG = 0x0a,
39 GIF_REG_XYZF3 = 0x0c,
40 GIF_REG_XYZ3 = 0x0d,
41 GIF_REG_A_D = 0x0e,
42 GIF_REG_NOP = 0x0f,
43 };
44
45 enum GIF_A_D_REG
46 {
47 GIF_A_D_REG_PRIM = 0x00,
48 GIF_A_D_REG_RGBAQ = 0x01,
49 GIF_A_D_REG_ST = 0x02,
50 GIF_A_D_REG_UV = 0x03,
51 GIF_A_D_REG_XYZF2 = 0x04,
52 GIF_A_D_REG_XYZ2 = 0x05,
53 GIF_A_D_REG_TEX0_1 = 0x06,
54 GIF_A_D_REG_TEX0_2 = 0x07,
55 GIF_A_D_REG_CLAMP_1 = 0x08,
56 GIF_A_D_REG_CLAMP_2 = 0x09,
57 GIF_A_D_REG_FOG = 0x0a,
58 GIF_A_D_REG_XYZF3 = 0x0c,
59 GIF_A_D_REG_XYZ3 = 0x0d,
60 GIF_A_D_REG_NOP = 0x0f,
61 GIF_A_D_REG_TEX1_1 = 0x14,
62 GIF_A_D_REG_TEX1_2 = 0x15,
63 GIF_A_D_REG_TEX2_1 = 0x16,
64 GIF_A_D_REG_TEX2_2 = 0x17,
65 GIF_A_D_REG_XYOFFSET_1 = 0x18,
66 GIF_A_D_REG_XYOFFSET_2 = 0x19,
67 GIF_A_D_REG_PRMODECONT = 0x1a,
68 GIF_A_D_REG_PRMODE = 0x1b,
69 GIF_A_D_REG_TEXCLUT = 0x1c,
70 GIF_A_D_REG_SCANMSK = 0x22,
71 GIF_A_D_REG_MIPTBP1_1 = 0x34,
72 GIF_A_D_REG_MIPTBP1_2 = 0x35,
73 GIF_A_D_REG_MIPTBP2_1 = 0x36,
74 GIF_A_D_REG_MIPTBP2_2 = 0x37,
75 GIF_A_D_REG_TEXA = 0x3b,
76 GIF_A_D_REG_FOGCOL = 0x3d,
77 GIF_A_D_REG_TEXFLUSH = 0x3f,
78 GIF_A_D_REG_SCISSOR_1 = 0x40,
79 GIF_A_D_REG_SCISSOR_2 = 0x41,
80 GIF_A_D_REG_ALPHA_1 = 0x42,
81 GIF_A_D_REG_ALPHA_2 = 0x43,
82 GIF_A_D_REG_DIMX = 0x44,
83 GIF_A_D_REG_DTHE = 0x45,
84 GIF_A_D_REG_COLCLAMP = 0x46,
85 GIF_A_D_REG_TEST_1 = 0x47,
86 GIF_A_D_REG_TEST_2 = 0x48,
87 GIF_A_D_REG_PABE = 0x49,
88 GIF_A_D_REG_FBA_1 = 0x4a,
89 GIF_A_D_REG_FBA_2 = 0x4b,
90 GIF_A_D_REG_FRAME_1 = 0x4c,
91 GIF_A_D_REG_FRAME_2 = 0x4d,
92 GIF_A_D_REG_ZBUF_1 = 0x4e,
93 GIF_A_D_REG_ZBUF_2 = 0x4f,
94 GIF_A_D_REG_BITBLTBUF = 0x50,
95 GIF_A_D_REG_TRXPOS = 0x51,
96 GIF_A_D_REG_TRXREG = 0x52,
97 GIF_A_D_REG_TRXDIR = 0x53,
98 GIF_A_D_REG_HWREG = 0x54,
99 GIF_A_D_REG_SIGNAL = 0x60,
100 GIF_A_D_REG_FINISH = 0x61,
101 GIF_A_D_REG_LABEL = 0x62,
102 };
103
104 // In case we want to change to/from __fastcall for GIF register handlers:
105 #define __gifCall __fastcall
106
107 typedef void __gifCall FnType_GIFRegHandler(const u32* data);
108 typedef FnType_GIFRegHandler* GIFRegHandler;
109
110 extern FnType_GIFRegHandler GIFPackedRegHandlerNull;
111 extern FnType_GIFRegHandler GIFPackedRegHandlerRGBA;
112 extern FnType_GIFRegHandler GIFPackedRegHandlerSTQ;
113 extern FnType_GIFRegHandler GIFPackedRegHandlerUV;
114 extern FnType_GIFRegHandler GIFPackedRegHandlerXYZF2;
115 extern FnType_GIFRegHandler GIFPackedRegHandlerXYZ2;
116 extern FnType_GIFRegHandler GIFPackedRegHandlerFOG;
117 extern FnType_GIFRegHandler GIFPackedRegHandlerA_D;
118 extern FnType_GIFRegHandler GIFPackedRegHandlerNOP;
119 extern FnType_GIFRegHandler GIFPackedRegHandlerPRIM;
120 extern FnType_GIFRegHandler GIFPackedRegHandlerXYZF3;
121 extern FnType_GIFRegHandler GIFPackedRegHandlerXYZ3;
122
123 extern FnType_GIFRegHandler GIFRegHandlerNull;
124 extern FnType_GIFRegHandler GIFRegHandlerPRIM;
125 extern FnType_GIFRegHandler GIFRegHandlerRGBAQ;
126 extern FnType_GIFRegHandler GIFRegHandlerST;
127 extern FnType_GIFRegHandler GIFRegHandlerUV;
128 extern FnType_GIFRegHandler GIFRegHandlerXYZF2;
129 extern FnType_GIFRegHandler GIFRegHandlerXYZ2;
130 extern FnType_GIFRegHandler GIFRegHandlerFOG;
131 extern FnType_GIFRegHandler GIFRegHandlerXYZF3;
132 extern FnType_GIFRegHandler GIFRegHandlerXYZ3;
133 extern FnType_GIFRegHandler GIFRegHandlerNOP;
134 extern FnType_GIFRegHandler GIFRegHandlerPRMODECONT;
135 extern FnType_GIFRegHandler GIFRegHandlerPRMODE;
136 extern FnType_GIFRegHandler GIFRegHandlerTEXCLUT;
137 extern FnType_GIFRegHandler GIFRegHandlerSCANMSK;
138 extern FnType_GIFRegHandler GIFRegHandlerTEXA;
139 extern FnType_GIFRegHandler GIFRegHandlerFOGCOL;
140 extern FnType_GIFRegHandler GIFRegHandlerTEXFLUSH;
141 extern FnType_GIFRegHandler GIFRegHandlerDIMX;
142 extern FnType_GIFRegHandler GIFRegHandlerDTHE;
143 extern FnType_GIFRegHandler GIFRegHandlerCOLCLAMP;
144 extern FnType_GIFRegHandler GIFRegHandlerPABE;
145 extern FnType_GIFRegHandler GIFRegHandlerBITBLTBUF;
146 extern FnType_GIFRegHandler GIFRegHandlerTRXPOS;
147 extern FnType_GIFRegHandler GIFRegHandlerTRXREG;
148 extern FnType_GIFRegHandler GIFRegHandlerTRXDIR;
149 extern FnType_GIFRegHandler GIFRegHandlerHWREG;
150 extern FnType_GIFRegHandler GIFRegHandlerSIGNAL;
151 extern FnType_GIFRegHandler GIFRegHandlerFINISH;
152 extern FnType_GIFRegHandler GIFRegHandlerLABEL;
153
154 template<u32 ctxt>
155 extern FnType_GIFRegHandler GIFPackedRegHandlerTEX0;
156 template<u32 ctxt>
157 extern FnType_GIFRegHandler GIFPackedRegHandlerCLAMP;
158 template<u32 ctxt>
159
160 extern FnType_GIFRegHandler GIFRegHandlerTEX0;
161 template<u32 ctxt>
162 extern FnType_GIFRegHandler GIFRegHandlerCLAMP;
163 template<u32 ctxt>
164 extern FnType_GIFRegHandler GIFRegHandlerTEX1;
165 template<u32 ctxt>
166 extern FnType_GIFRegHandler GIFRegHandlerTEX2;
167 template<u32 ctxt>
168 extern FnType_GIFRegHandler GIFRegHandlerXYOFFSET;
169 template<u32 ctxt>
170 extern FnType_GIFRegHandler GIFRegHandlerMIPTBP1;
171 template<u32 ctxt>
172 extern FnType_GIFRegHandler GIFRegHandlerMIPTBP2;
173 template<u32 ctxt>
174 extern FnType_GIFRegHandler GIFRegHandlerSCISSOR;
175 template<u32 ctxt>
176 extern FnType_GIFRegHandler GIFRegHandlerALPHA;
177 template<u32 ctxt>
178 extern FnType_GIFRegHandler GIFRegHandlerTEST;
179 template<u32 ctxt>
180 extern FnType_GIFRegHandler GIFRegHandlerFBA;
181 template<u32 ctxt>
182 extern FnType_GIFRegHandler GIFRegHandlerFRAME;
183 template<u32 ctxt>
184 extern FnType_GIFRegHandler GIFRegHandlerZBUF;
185
186 // GifReg & GifPackedReg structs from GSdx, slightly modified.
187 enum GS_ATST
188 {
189 ATST_NEVER = 0,
190 ATST_ALWAYS = 1,
191 ATST_LESS = 2,
192 ATST_LEQUAL = 3,
193 ATST_EQUAL = 4,
194 ATST_GEQUAL = 5,
195 ATST_GREATER = 6,
196 ATST_NOTEQUAL = 7,
197 };
198
199 enum GS_AFAIL
200 {
201 AFAIL_KEEP = 0,
202 AFAIL_FB_ONLY = 1,
203 AFAIL_ZB_ONLY = 2,
204 AFAIL_RGB_ONLY = 3,
205 };
206
207 // GIFReg
208
209 REG64_(GIFReg, ALPHA)
210 u32 A:2;
211 u32 B:2;
212 u32 C:2;
213 u32 D:2;
214 u32 _PAD1:24;
215 u32 FIX:8;
216 u32 _PAD2:24;
217 REG_END2
218 // opaque => output will be Cs/As
219 // __forceinline bool IsOpaque() const {return (A == B || C == 2 && FIX == 0) && D == 0 || (A == 0 && B == D && C == 2 && FIX == 0x80);}
220 // __forceinline bool IsOpaque(int amin, int amax) const {return (A == B || amax == 0) && D == 0 || A == 0 && B == D && amin == 0x80 && amax == 0x80;}
221 REG_END2
222
223 REG64_(GIFReg, BITBLTBUF)
224 u32 SBP:14;
225 u32 _PAD1:2;
226 u32 SBW:6;
227 u32 _PAD2:2;
228 u32 SPSM:6;
229 u32 _PAD3:2;
230 u32 DBP:14;
231 u32 _PAD4:2;
232 u32 DBW:6;
233 u32 _PAD5:2;
234 u32 DPSM:6;
235 u32 _PAD6:2;
236 REG_END
237
238 REG64_(GIFReg, CLAMP)
239 union
240 {
241 struct
242 {
243 u32 WMS:2;
244 u32 WMT:2;
245 u32 MINU:10;
246 u32 MAXU:10;
247 u32 _PAD1:8;
248 u32 _PAD2:2;
249 u32 MAXV:10;
250 u32 _PAD3:20;
251 };
252
253 struct
254 {
255 u64 _PAD4:24;
256 u64 MINV:10;
257 u64 _PAD5:30;
258 };
259 };
260 REG_END
261
262 REG64_(GIFReg, COLCLAMP)
263 u32 CLAMP:1;
264 u32 _PAD1:31;
265 u32 _PAD2:32;
266 REG_END
267
268 REG64_(GIFReg, DIMX)
269 s32 DM00:3;
270 s32 _PAD00:1;
271 s32 DM01:3;
272 s32 _PAD01:1;
273 s32 DM02:3;
274 s32 _PAD02:1;
275 s32 DM03:3;
276 s32 _PAD03:1;
277 s32 DM10:3;
278 s32 _PAD10:1;
279 s32 DM11:3;
280 s32 _PAD11:1;
281 s32 DM12:3;
282 s32 _PAD12:1;
283 s32 DM13:3;
284 s32 _PAD13:1;
285 s32 DM20:3;
286 s32 _PAD20:1;
287 s32 DM21:3;
288 s32 _PAD21:1;
289 s32 DM22:3;
290 s32 _PAD22:1;
291 s32 DM23:3;
292 s32 _PAD23:1;
293 s32 DM30:3;
294 s32 _PAD30:1;
295 s32 DM31:3;
296 s32 _PAD31:1;
297 s32 DM32:3;
298 s32 _PAD32:1;
299 s32 DM33:3;
300 s32 _PAD33:1;
301 REG_END
302
303 REG64_(GIFReg, DTHE)
304 u32 DTHE:1;
305 u32 _PAD1:31;
306 u32 _PAD2:32;
307 REG_END
308
309 REG64_(GIFReg, FBA)
310 u32 FBA:1;
311 u32 _PAD1:31;
312 u32 _PAD2:32;
313 REG_END
314
315 REG64_(GIFReg, FINISH)
316 u32 _PAD1:32;
317 u32 _PAD2:32;
318 REG_END
319
320 REG64_(GIFReg, FOG)
321 u32 _PAD1:32;
322 u32 _PAD2:24;
323 u32 F:8;
324 REG_END
325
326 REG64_(GIFReg, FOGCOL)
327 u32 FCR:8;
328 u32 FCG:8;
329 u32 FCB:8;
330 u32 _PAD1:8;
331 u32 _PAD2:32;
332 REG_END
333
334 REG64_(GIFReg, FRAME)
335 u32 FBP:9;
336 u32 _PAD1:7;
337 u32 FBW:6;
338 u32 _PAD2:2;
339 u32 PSM:6;
340 u32 _PAD3:2;
341 u32 FBMSK:32;
342 REG_END2
343 u32 Block() const {return FBP << 5;}
344 REG_END2
345
346 REG64_(GIFReg, HWREG)
347 u32 DATA_LOWER:32;
348 u32 DATA_UPPER:32;
349 REG_END
350
351 REG64_(GIFReg, LABEL)
352 u32 ID:32;
353 u32 IDMSK:32;
354 REG_END
355
356 REG64_(GIFReg, MIPTBP1)
357 u64 TBP1:14;
358 u64 TBW1:6;
359 u64 TBP2:14;
360 u64 TBW2:6;
361 u64 TBP3:14;
362 u64 TBW3:6;
363 u64 _PAD:4;
364 REG_END
365
366 REG64_(GIFReg, MIPTBP2)
367 u64 TBP4:14;
368 u64 TBW4:6;
369 u64 TBP5:14;
370 u64 TBW5:6;
371 u64 TBP6:14;
372 u64 TBW6:6;
373 u64 _PAD:4;
374 REG_END
375
376 REG64_(GIFReg, NOP)
377 u32 _PAD1:32;
378 u32 _PAD2:32;
379 REG_END
380
381 REG64_(GIFReg, PABE)
382 u32 PABE:1;
383 u32 _PAD1:31;
384 u32 _PAD2:32;
385 REG_END
386
387 REG64_(GIFReg, PRIM)
388 u32 PRIM:3;
389 u32 IIP:1;
390 u32 TME:1;
391 u32 FGE:1;
392 u32 ABE:1;
393 u32 AA1:1;
394 u32 FST:1;
395 u32 CTXT:1;
396 u32 FIX:1;
397 u32 _PAD1:21;
398 u32 _PAD2:32;
399 REG_END
400
401 REG64_(GIFReg, PRMODE)
402 u32 _PRIM:3;
403 u32 IIP:1;
404 u32 TME:1;
405 u32 FGE:1;
406 u32 ABE:1;
407 u32 AA1:1;
408 u32 FST:1;
409 u32 CTXT:1;
410 u32 FIX:1;
411 u32 _PAD2:21;
412 u32 _PAD3:32;
413 REG_END
414
415 REG64_(GIFReg, PRMODECONT)
416 u32 AC:1;
417 u32 _PAD1:31;
418 u32 _PAD2:32;
419 REG_END
420
421 REG64_(GIFReg, RGBAQ)
422 u32 R:8;
423 u32 G:8;
424 u32 B:8;
425 u32 A:8;
426 float Q;
427 REG_END
428
429 REG64_(GIFReg, SCANMSK)
430 u32 MSK:2;
431 u32 _PAD1:30;
432 u32 _PAD2:32;
433 REG_END
434
435 REG64_(GIFReg, SCISSOR)
436 u32 SCAX0:11;
437 u32 _PAD1:5;
438 u32 SCAX1:11;
439 u32 _PAD2:5;
440 u32 SCAY0:11;
441 u32 _PAD3:5;
442 u32 SCAY1:11;
443 u32 _PAD4:5;
444 REG_END
445
446 REG64_(GIFReg, SIGNAL)
447 u32 ID:32;
448 u32 IDMSK:32;
449 REG_END
450
451 REG64_(GIFReg, ST)
452 float S;
453 float T;
454 REG_END
455
456 REG64_(GIFReg, TEST)
457 u32 ATE:1;
458 u32 ATST:3;
459 u32 AREF:8;
460 u32 AFAIL:2;
461 u32 DATE:1;
462 u32 DATM:1;
463 u32 ZTE:1;
464 u32 ZTST:2;
465 u32 _PAD1:13;
466 u32 _PAD2:32;
467 REG_END2
468 __forceinline bool DoFirstPass() {return !ATE || ATST != ATST_NEVER;} // not all pixels fail automatically
469 __forceinline bool DoSecondPass() {return ATE && ATST != ATST_ALWAYS && AFAIL != AFAIL_KEEP;} // pixels may fail, write fb/z
470 __forceinline bool NoSecondPass() {return ATE && ATST != ATST_ALWAYS && AFAIL == AFAIL_KEEP;} // pixels may fail, no output
471 REG_END2
472
473 REG64_(GIFReg, TEX0)
474 union
475 {
476 struct
477 {
478 u32 TBP0:14;
479 u32 TBW:6;
480 u32 PSM:6;
481 u32 TW:4;
482 u32 _PAD1:2;
483 u32 _PAD2:2;
484 u32 TCC:1;
485 u32 TFX:2;
486 u32 CBP:14;
487 u32 CPSM:4;
488 u32 CSM:1;
489 u32 CSA:5;
490 u32 CLD:3;
491 };
492
493 struct
494 {
495 u64 _PAD3:30;
496 u64 TH:4;
497 u64 _PAD4:30;
498 };
499 };
500 REG_END2
501 __forceinline bool IsRepeating() {return (u32)((u32)1 << TW) > (u32)(TBW << (u32)6);}
502 REG_END2
503
504 REG64_(GIFReg, TEX1)
505 u32 LCM:1;
506 u32 _PAD1:1;
507 u32 MXL:3;
508 u32 MMAG:1;
509 u32 MMIN:3;
510 u32 MTBA:1;
511 u32 _PAD2:9;
512 u32 L:2;
513 u32 _PAD3:11;
514 s32 K:12; // 1:7:4
515 u32 _PAD4:20;
516 REG_END2
517 bool IsMinLinear() const {return (MMIN == 1) || (MMIN & 4);}
518 bool IsMagLinear() const {return MMAG;}
519 REG_END2
520
521 REG64_(GIFReg, TEX2)
522 u32 _PAD1:20;
523 u32 PSM:6;
524 u32 _PAD2:6;
525 u32 _PAD3:5;
526 u32 CBP:14;
527 u32 CPSM:4;
528 u32 CSM:1;
529 u32 CSA:5;
530 u32 CLD:3;
531 REG_END
532
533 REG64_(GIFReg, TEXA)
534 u32 TA0:8;
535 u32 _PAD1:7;
536 u32 AEM:1;
537 u32 _PAD2:16;
538 u32 TA1:8;
539 u32 _PAD3:24;
540 REG_END
541
542 REG64_(GIFReg, TEXCLUT)
543 u32 CBW:6;
544 u32 COU:6;
545 u32 COV:10;
546 u32 _PAD1:10;
547 u32 _PAD2:32;
548 REG_END
549
550 REG64_(GIFReg, TEXFLUSH)
551 u32 _PAD1:32;
552 u32 _PAD2:32;
553 REG_END
554
555 REG64_(GIFReg, TRXDIR)
556 u32 XDIR:2;
557 u32 _PAD1:30;
558 u32 _PAD2:32;
559 REG_END
560
561 REG64_(GIFReg, TRXPOS)
562 u32 SSAX:11;
563 u32 _PAD1:5;
564 u32 SSAY:11;
565 u32 _PAD2:5;
566 u32 DSAX:11;
567 u32 _PAD3:5;
568 u32 DSAY:11;
569 u32 DIRY:1;
570 u32 DIRX:1;
571 u32 _PAD4:3;
572 REG_END
573
574 REG64_(GIFReg, TRXREG)
575 u32 RRW:12;
576 u32 _PAD1:20;
577 u32 RRH:12;
578 u32 _PAD2:20;
579 REG_END
580
581 // GSState::GIFPackedRegHandlerUV and GSState::GIFRegHandlerUV will make sure that the _PAD1/2 bits are set to zero
582
583 REG64_(GIFReg, UV)
584 u32 U:14;
585 u32 _PAD1:2;
586 u32 V:14;
587 u32 _PAD2:2;
588 u32 _PAD3:32;
589 REG_END
590
591 // GSState::GIFRegHandlerXYOFFSET will make sure that the _PAD1/2 bits are set to zero
592
593 REG64_(GIFReg, XYOFFSET)
594 u32 OFX; // :16; u32 _PAD1:16;
595 u32 OFY; // :16; u32 _PAD2:16;
596 REG_END
597
598 REG64_(GIFReg, XYZ)
599 u32 X:16;
600 u32 Y:16;
601 u32 Z:32;
602 REG_END
603
604 REG64_(GIFReg, XYZF)
605 u32 X:16;
606 u32 Y:16;
607 u32 Z:24;
608 u32 F:8;
609 REG_END
610
611 REG64_(GIFReg, ZBUF)
612 u32 ZBP:9;
613 u32 _PAD1:15;
614 // u32 PSM:4;
615 // u32 _PAD2:4;
616 u32 PSM:6;
617 u32 _PAD2:2;
618 u32 ZMSK:1;
619 u32 _PAD3:31;
620 REG_END2
621 u32 Block() const {return ZBP << 5;}
622 REG_END2
623
624 REG64_SET(GIFReg)
625 GIFRegALPHA ALPHA;
626 GIFRegBITBLTBUF BITBLTBUF;
627 GIFRegCLAMP CLAMP;
628 GIFRegCOLCLAMP COLCLAMP;
629 GIFRegDIMX DIMX;
630 GIFRegDTHE DTHE;
631 GIFRegFBA FBA;
632 GIFRegFINISH FINISH;
633 GIFRegFOG FOG;
634 GIFRegFOGCOL FOGCOL;
635 GIFRegFRAME FRAME;
636 GIFRegHWREG HWREG;
637 GIFRegLABEL LABEL;
638 GIFRegMIPTBP1 MIPTBP1;
639 GIFRegMIPTBP2 MIPTBP2;
640 GIFRegNOP NOP;
641 GIFRegPABE PABE;
642 GIFRegPRIM PRIM;
643 GIFRegPRMODE PRMODE;
644 GIFRegPRMODECONT PRMODECONT;
645 GIFRegRGBAQ RGBAQ;
646 GIFRegSCANMSK SCANMSK;
647 GIFRegSCISSOR SCISSOR;
648 GIFRegSIGNAL SIGNAL;
649 GIFRegST ST;
650 GIFRegTEST TEST;
651 GIFRegTEX0 TEX0;
652 GIFRegTEX1 TEX1;
653 GIFRegTEX2 TEX2;
654 GIFRegTEXA TEXA;
655 GIFRegTEXCLUT TEXCLUT;
656 GIFRegTEXFLUSH TEXFLUSH;
657 GIFRegTRXDIR TRXDIR;
658 GIFRegTRXPOS TRXPOS;
659 GIFRegTRXREG TRXREG;
660 GIFRegUV UV;
661 GIFRegXYOFFSET XYOFFSET;
662 GIFRegXYZ XYZ;
663 GIFRegXYZF XYZF;
664 GIFRegZBUF ZBUF;
665 REG_SET_END
666
667 // GIFPacked
668
669 REG128_(GIFPacked, PRIM)
670 u32 PRIM:11;
671 u32 _PAD1:21;
672 u32 _PAD2:32;
673 u32 _PAD3:32;
674 u32 _PAD4:32;
675 REG_END
676
677 REG128_(GIFPacked, RGBA)
678 u32 R:8;
679 u32 _PAD1:24;
680 u32 G:8;
681 u32 _PAD2:24;
682 u32 B:8;
683 u32 _PAD3:24;
684 u32 A:8;
685 u32 _PAD4:24;
686 REG_END
687
688 REG128_(GIFPacked, STQ)
689 float S;
690 float T;
691 float Q;
692 u32 _PAD1:32;
693 REG_END
694
695 REG128_(GIFPacked, UV)
696 u32 U:14;
697 u32 _PAD1:18;
698 u32 V:14;
699 u32 _PAD2:18;
700 u32 _PAD3:32;
701 u32 _PAD4:32;
702 REG_END
703
704 REG128_(GIFPacked, XYZF2)
705 u32 X:16;
706 u32 _PAD1:16;
707 u32 Y:16;
708 u32 _PAD2:16;
709 u32 _PAD3:4;
710 u32 Z:24;
711 u32 _PAD4:4;
712 u32 _PAD5:4;
713 u32 F:8;
714 u32 _PAD6:3;
715 u32 ADC:1;
716 u32 _PAD7:16;
717 REG_END
718
719 REG128_(GIFPacked, XYZ2)
720 u32 X:16;
721 u32 _PAD1:16;
722 u32 Y:16;
723 u32 _PAD2:16;
724 u32 Z:32;
725 u32 _PAD3:15;
726 u32 ADC:1;
727 u32 _PAD4:16;
728 REG_END
729
730 REG128_(GIFPacked, FOG)
731 u32 _PAD1:32;
732 u32 _PAD2:32;
733 u32 _PAD3:32;
734 u32 _PAD4:4;
735 u32 F:8;
736 u32 _PAD5:20;
737 REG_END
738
739 REG128_(GIFPacked, A_D)
740 u64 DATA:64;
741 u32 ADDR:8; // enum GIF_A_D_REG
742 u32 _PAD1:24;
743 u32 _PAD2:32;
744 REG_END
745
746 REG128_(GIFPacked, NOP)
747 u32 _PAD1:32;
748 u32 _PAD2:32;
749 u32 _PAD3:32;
750 u32 _PAD4:32;
751 REG_END
752
753 REG128_SET(GIFPackedReg)
754 GIFReg r;
755 GIFPackedPRIM PRIM;
756 GIFPackedRGBA RGBA;
757 GIFPackedSTQ STQ;
758 GIFPackedUV UV;
759 GIFPackedXYZF2 XYZF2;
760 GIFPackedXYZ2 XYZ2;
761 GIFPackedFOG FOG;
762 GIFPackedA_D A_D;
763 GIFPackedNOP NOP;
764 REG_SET_END
765
766
767 REG64_(GSReg, BGCOLOR)
768 u32 R:8;
769 u32 G:8;
770 u32 B:8;
771 u32 _PAD1:8;
772 u32 _PAD2:32;
773 REG_END
774
775 REG64_(GSReg, BUSDIR)
776 u32 DIR:1;
777 u32 _PAD1:31;
778 u32 _PAD2:32;
779 REG_END
780
781 REG64_(GSReg, CSR)
782 u32 SIGNAL:1;
783 u32 FINISH:1;
784 u32 HSINT:1;
785 u32 VSINT:1;
786 u32 EDWINT:1;
787 u32 ZERO1:1;
788 u32 ZERO2:1;
789 u32 _PAD1:1;
790 u32 FLUSH:1;
791 u32 RESET:1;
792 u32 _PAD2:2;
793 u32 NFIELD:1;
794 u32 FIELD:1;
795 u32 FIFO:2;
796 u32 REV:8;
797 u32 ID:8;
798 u32 _PAD3:32;
799 REG_END
800
801 REG64_(GSReg, DISPFB) // (-1/2)
802 u32 FBP:9;
803 u32 FBW:6;
804 u32 PSM:5;
805 u32 _PAD:12;
806 u32 DBX:11;
807 u32 DBY:11;
808 u32 _PAD2:10;
809 REG_END
810
811 REG64_(GSReg, DISPLAY) // (-1/2)
812 u32 DX:12;
813 u32 DY:11;
814 u32 MAGH:4;
815 u32 MAGV:2;
816 u32 _PAD:3;
817 u32 DW:12;
818 u32 DH:11;
819 u32 _PAD2:9;
820 REG_END
821
822 REG64_(GSReg, EXTBUF)
823 u32 EXBP:14;
824 u32 EXBW:6;
825 u32 FBIN:2;
826 u32 WFFMD:1;
827 u32 EMODA:2;
828 u32 EMODC:2;
829 u32 _PAD1:5;
830 u32 WDX:11;
831 u32 WDY:11;
832 u32 _PAD2:10;
833 REG_END
834
835 REG64_(GSReg, EXTDATA)
836 u32 SX:12;
837 u32 SY:11;
838 u32 SMPH:4;
839 u32 SMPV:2;
840 u32 _PAD1:3;
841 u32 WW:12;
842 u32 WH:11;
843 u32 _PAD2:9;
844 REG_END
845
846 REG64_(GSReg, EXTWRITE)
847 u32 WRITE;
848 u32 _PAD2:32;
849 REG_END
850
851 REG64_(GSReg, IMR)
852 u32 _PAD1:8;
853 u32 SIGMSK:1;
854 u32 FINISHMSK:1;
855 u32 HSMSK:1;
856 u32 VSMSK:1;
857 u32 EDWMSK:1;
858 u32 _PAD2:19;
859 u32 _PAD3:32;
860 REG_END
861
862 REG64_(GSReg, PMODE)
863 u32 EN1:1;
864 u32 EN2:1;
865 u32 CRTMD:3;
866 u32 MMOD:1;
867 u32 AMOD:1;
868 u32 SLBG:1;
869 u32 ALP:8;
870 u32 _PAD:16;
871 u32 _PAD1:32;
872 REG_END
873
874 REG64_(GSReg, SIGLBLID)
875 u32 SIGID:32;
876 u32 LBLID:32;
877 REG_END
878
879 REG64_(GSReg, SMODE1)
880 u32 RC:3;
881 u32 LC:7;
882 u32 T1248:2;
883 u32 SLCK:1;
884 u32 CMOD:2;
885 u32 EX:1;
886 u32 PRST:1;
887 u32 SINT:1;
888 u32 XPCK:1;
889 u32 PCK2:2;
890 u32 SPML:4;
891 u32 GCONT:1;
892 u32 PHS:1;
893 u32 PVS:1;
894 u32 PEHS:1;
895 u32 PEVS:1;
896 u32 CLKSEL:2;
897 u32 NVCK:1;
898 u32 SLCK2:1;
899 u32 VCKSEL:2;
900 u32 VHP:1;
901 u32 _PAD1:27;
902 REG_END
903
904 REG64_(GSReg, SMODE2)
905 u32 INT:1;
906 u32 FFMD:1;
907 u32 DPMS:2;
908 u32 _PAD2:28;
909 u32 _PAD3:32;
910 REG_END
911
912 REG64_(GSReg, SIGBLID)
913 u32 SIGID;
914 u32 LBLID;
915 REG_END
916
917 #define PMODE ((GSRegPMODE*)(g_pBasePS2Mem+0x0000))
918 #define SMODE1 ((GSRegSMODE1*)(g_pBasePS2Mem+0x0010))
919 #define SMODE2 ((GSRegSMODE2*)(g_pBasePS2Mem+0x0020))
920 // SRFSH
921 #define SYNCH1 ((GSRegSYNCH1*)(g_pBasePS2Mem+0x0040))
922 #define SYNCH2 ((GSRegSYNCH2*)(g_pBasePS2Mem+0x0050))
923 #define SYNCV ((GSRegSYNCV*)(g_pBasePS2Mem+0x0060))
924 #define DISPFB1 ((GSRegDISPFB*)(g_pBasePS2Mem+0x0070))
925 #define DISPLAY1 ((GSRegDISPLAY*)(g_pBasePS2Mem+0x0080))
926 #define DISPFB2 ((GSRegDISPFB*)(g_pBasePS2Mem+0x0090))
927 #define DISPLAY2 ((GSRegDISPLAY*)(g_pBasePS2Mem+0x00a0))
928 #define EXTBUF ((GSRegEXTBUF*)(g_pBasePS2Mem+0x00b0))
929 #define EXTDATA ((GSRegEXTDATA*)(g_pBasePS2Mem+0x00c0))
930 #define EXTWRITE ((GSRegEXTWRITE*)(g_pBasePS2Mem+0x00d0))
931 #define BGCOLOR ((GSRegBGCOLOR*)(g_pBasePS2Mem+0x00e0))
932 #define CSR ((GSRegCSR*)(g_pBasePS2Mem+0x1000))
933 #define IMR ((GSRegIMR*)(g_pBasePS2Mem+0x1010))
934 #define BUSDIR ((GSRegBUSDIR*)(g_pBasePS2Mem+0x1040))
935 #define SIGLBLID ((GSRegSIGBLID*)(g_pBasePS2Mem+0x1080))
936
937 //
938 // sps2tags.h
939 //
940 #define GET_GIF_REG(tag, reg) \
941 (((tag).ai32[2 + ((reg) >> 3)] >> (((reg) & 7) << 2)) & 0xf)
942
943 #define GET_GSFPS (((SMODE1->CMOD&1) ? 50 : 60) / (SMODE2->INT ? 1 : 2))
944
945 extern void WriteTempRegs();
946 extern void SetFrameSkip(bool skip);
947 extern void ResetRegs();
948
949 extern void SetTexFlush();
950 extern void SetFogColor(u32 fog);
951 extern void SetFogColor(GIFRegFOGCOL* fog);
952 extern bool CheckChangeInClut(u32 highdword, u32 psm); // returns true if clut will change after this tex0 op
953
954 // flush current vertices, call before setting new registers (the main render method)
955 void Flush(int context);
956 void FlushBoth();
957
958 // called on a primitive switch
959 void Prim();
960
961 #else
962 #include "NewRegs.h"
963 #endif
964 #endif

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