/[pcsx2_0.9.7]/branch/debug/0.X/0.9.X/0.9.7/ramdump-lateset/plugins/zzogl-pg/opengl/NewRegs.h
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Contents of /branch/debug/0.X/0.9.X/0.9.7/ramdump-lateset/plugins/zzogl-pg/opengl/NewRegs.h

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Revision 314 - (show annotations) (download)
Sun Dec 26 18:56:19 2010 UTC (9 years, 2 months ago) by william
File MIME type: text/plain
File size: 18303 byte(s)
** merged upstream r4049 (re-integration of GregMiscellaneous branch)
** applied patched to GigTranser.cpp in ZZOgl from r4140 to change 'static int count = 0;' to 'static int path1_count = 0;')
1 /* ZZ Open GL graphics plugin
2 * Copyright (c)2009-2010 zeydlitz@gmail.com, arcum42@gmail.com
3 * Based on Zerofrog's ZeroGS KOSMOS (c)2005-2008
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
18 */
19
20 #ifndef NEWREGS_H_INCLUDED
21 #define NEWREGS_H_INCLUDED
22
23 #ifdef USE_OLD_REGS
24 #include "Regs.h"
25 #else
26
27 enum GIF_REG
28 {
29 GIF_REG_PRIM = 0x00,
30 GIF_REG_RGBA = 0x01,
31 GIF_REG_STQ = 0x02,
32 GIF_REG_UV = 0x03,
33 GIF_REG_XYZF2 = 0x04,
34 GIF_REG_XYZ2 = 0x05,
35 GIF_REG_TEX0_1 = 0x06,
36 GIF_REG_TEX0_2 = 0x07,
37 GIF_REG_CLAMP_1 = 0x08,
38 GIF_REG_CLAMP_2 = 0x09,
39 GIF_REG_FOG = 0x0a,
40 GIF_REG_XYZF3 = 0x0c,
41 GIF_REG_XYZ3 = 0x0d,
42 GIF_REG_A_D = 0x0e,
43 GIF_REG_NOP = 0x0f,
44 };
45
46 enum GIF_A_D_REG
47 {
48 GIF_A_D_REG_PRIM = 0x00,
49 GIF_A_D_REG_RGBAQ = 0x01,
50 GIF_A_D_REG_ST = 0x02,
51 GIF_A_D_REG_UV = 0x03,
52 GIF_A_D_REG_XYZF2 = 0x04,
53 GIF_A_D_REG_XYZ2 = 0x05,
54 GIF_A_D_REG_TEX0_1 = 0x06,
55 GIF_A_D_REG_TEX0_2 = 0x07,
56 GIF_A_D_REG_CLAMP_1 = 0x08,
57 GIF_A_D_REG_CLAMP_2 = 0x09,
58 GIF_A_D_REG_FOG = 0x0a,
59 GIF_A_D_REG_XYZF3 = 0x0c,
60 GIF_A_D_REG_XYZ3 = 0x0d,
61 GIF_A_D_REG_NOP = 0x0f,
62 GIF_A_D_REG_TEX1_1 = 0x14,
63 GIF_A_D_REG_TEX1_2 = 0x15,
64 GIF_A_D_REG_TEX2_1 = 0x16,
65 GIF_A_D_REG_TEX2_2 = 0x17,
66 GIF_A_D_REG_XYOFFSET_1 = 0x18,
67 GIF_A_D_REG_XYOFFSET_2 = 0x19,
68 GIF_A_D_REG_PRMODECONT = 0x1a,
69 GIF_A_D_REG_PRMODE = 0x1b,
70 GIF_A_D_REG_TEXCLUT = 0x1c,
71 GIF_A_D_REG_SCANMSK = 0x22,
72 GIF_A_D_REG_MIPTBP1_1 = 0x34,
73 GIF_A_D_REG_MIPTBP1_2 = 0x35,
74 GIF_A_D_REG_MIPTBP2_1 = 0x36,
75 GIF_A_D_REG_MIPTBP2_2 = 0x37,
76 GIF_A_D_REG_TEXA = 0x3b,
77 GIF_A_D_REG_FOGCOL = 0x3d,
78 GIF_A_D_REG_TEXFLUSH = 0x3f,
79 GIF_A_D_REG_SCISSOR_1 = 0x40,
80 GIF_A_D_REG_SCISSOR_2 = 0x41,
81 GIF_A_D_REG_ALPHA_1 = 0x42,
82 GIF_A_D_REG_ALPHA_2 = 0x43,
83 GIF_A_D_REG_DIMX = 0x44,
84 GIF_A_D_REG_DTHE = 0x45,
85 GIF_A_D_REG_COLCLAMP = 0x46,
86 GIF_A_D_REG_TEST_1 = 0x47,
87 GIF_A_D_REG_TEST_2 = 0x48,
88 GIF_A_D_REG_PABE = 0x49,
89 GIF_A_D_REG_FBA_1 = 0x4a,
90 GIF_A_D_REG_FBA_2 = 0x4b,
91 GIF_A_D_REG_FRAME_1 = 0x4c,
92 GIF_A_D_REG_FRAME_2 = 0x4d,
93 GIF_A_D_REG_ZBUF_1 = 0x4e,
94 GIF_A_D_REG_ZBUF_2 = 0x4f,
95 GIF_A_D_REG_BITBLTBUF = 0x50,
96 GIF_A_D_REG_TRXPOS = 0x51,
97 GIF_A_D_REG_TRXREG = 0x52,
98 GIF_A_D_REG_TRXDIR = 0x53,
99 GIF_A_D_REG_HWREG = 0x54,
100 GIF_A_D_REG_SIGNAL = 0x60,
101 GIF_A_D_REG_FINISH = 0x61,
102 GIF_A_D_REG_LABEL = 0x62,
103 };
104 // In case we want to change to/from __fastcall for GIF register handlers:
105 #define __gifCall __fastcall
106
107 typedef void __gifCall FnType_GIFRegHandler(const u32* data);
108 typedef FnType_GIFRegHandler* GIFRegHandler;
109
110 extern FnType_GIFRegHandler GIFPackedRegHandlerNull;
111 extern FnType_GIFRegHandler GIFPackedRegHandlerRGBA;
112 extern FnType_GIFRegHandler GIFPackedRegHandlerSTQ;
113 extern FnType_GIFRegHandler GIFPackedRegHandlerUV;
114 extern FnType_GIFRegHandler GIFPackedRegHandlerXYZF2;
115 extern FnType_GIFRegHandler GIFPackedRegHandlerXYZ2;
116 extern FnType_GIFRegHandler GIFPackedRegHandlerFOG;
117 extern FnType_GIFRegHandler GIFPackedRegHandlerA_D;
118 extern FnType_GIFRegHandler GIFPackedRegHandlerNOP;
119
120 // These are unimplemented, and fall back on the non-packed versions.
121 extern FnType_GIFRegHandler GIFPackedRegHandlerPRIM;
122
123 template<u32 i>
124 extern FnType_GIFRegHandler GIFPackedRegHandlerTEX0;
125
126 template<u32 i>
127 extern FnType_GIFRegHandler GIFPackedRegHandlerCLAMP;
128
129 extern FnType_GIFRegHandler GIFPackedRegHandlerXYZF3;
130 extern FnType_GIFRegHandler GIFPackedRegHandlerXYZ3;
131
132 extern FnType_GIFRegHandler GIFRegHandlerNull;
133 extern FnType_GIFRegHandler GIFRegHandlerPRIM;
134 extern FnType_GIFRegHandler GIFRegHandlerRGBAQ;
135 extern FnType_GIFRegHandler GIFRegHandlerST;
136 extern FnType_GIFRegHandler GIFRegHandlerUV;
137 extern FnType_GIFRegHandler GIFRegHandlerXYZF2;
138 extern FnType_GIFRegHandler GIFRegHandlerXYZ2;
139
140 template<u32 i>
141 extern FnType_GIFRegHandler GIFRegHandlerTEX0;
142
143 template<u32 i>
144 extern FnType_GIFRegHandler GIFRegHandlerCLAMP;
145
146 extern FnType_GIFRegHandler GIFRegHandlerFOG;
147 extern FnType_GIFRegHandler GIFRegHandlerXYZF3;
148 extern FnType_GIFRegHandler GIFRegHandlerXYZ3;
149 extern FnType_GIFRegHandler GIFRegHandlerNOP;
150
151 template <u32 i>
152 extern FnType_GIFRegHandler GIFRegHandlerTEX1;
153
154 template <u32 i>
155 extern FnType_GIFRegHandler GIFRegHandlerTEX2;
156
157 template <u32 i>
158 extern FnType_GIFRegHandler GIFRegHandlerXYOFFSET;
159
160 extern FnType_GIFRegHandler GIFRegHandlerPRMODECONT;
161 extern FnType_GIFRegHandler GIFRegHandlerPRMODE;
162 extern FnType_GIFRegHandler GIFRegHandlerTEXCLUT;
163 extern FnType_GIFRegHandler GIFRegHandlerSCANMSK;
164 template <u32 i>
165 extern FnType_GIFRegHandler GIFRegHandlerMIPTBP1;
166 template <u32 i>
167 extern FnType_GIFRegHandler GIFRegHandlerMIPTBP2;
168 extern FnType_GIFRegHandler GIFRegHandlerTEXA;
169 extern FnType_GIFRegHandler GIFRegHandlerFOGCOL;
170 extern FnType_GIFRegHandler GIFRegHandlerTEXFLUSH;
171
172 template <u32 i>
173 extern FnType_GIFRegHandler GIFRegHandlerSCISSOR;
174 template <u32 i>
175 extern FnType_GIFRegHandler GIFRegHandlerALPHA;
176
177 extern FnType_GIFRegHandler GIFRegHandlerDIMX;
178 extern FnType_GIFRegHandler GIFRegHandlerDTHE;
179 extern FnType_GIFRegHandler GIFRegHandlerCOLCLAMP;
180 template <u32 i>
181 extern FnType_GIFRegHandler GIFRegHandlerTEST;
182 extern FnType_GIFRegHandler GIFRegHandlerPABE;
183 template <u32 i>
184 extern FnType_GIFRegHandler GIFRegHandlerFBA;
185 template <u32 i>
186 extern FnType_GIFRegHandler GIFRegHandlerFRAME;
187 template <u32 i>
188 extern FnType_GIFRegHandler GIFRegHandlerZBUF;
189 extern FnType_GIFRegHandler GIFRegHandlerBITBLTBUF;
190 extern FnType_GIFRegHandler GIFRegHandlerTRXPOS;
191 extern FnType_GIFRegHandler GIFRegHandlerTRXREG;
192 extern FnType_GIFRegHandler GIFRegHandlerTRXDIR;
193 extern FnType_GIFRegHandler GIFRegHandlerHWREG;
194 extern FnType_GIFRegHandler GIFRegHandlerSIGNAL;
195 extern FnType_GIFRegHandler GIFRegHandlerFINISH;
196 extern FnType_GIFRegHandler GIFRegHandlerLABEL;
197
198 // GifReg & GifPackedReg structs from GSdx, slightly modified
199
200 enum GS_ATST
201 {
202 ATST_NEVER = 0,
203 ATST_ALWAYS = 1,
204 ATST_LESS = 2,
205 ATST_LEQUAL = 3,
206 ATST_EQUAL = 4,
207 ATST_GEQUAL = 5,
208 ATST_GREATER = 6,
209 ATST_NOTEQUAL = 7,
210 };
211
212 enum GS_AFAIL
213 {
214 AFAIL_KEEP = 0,
215 AFAIL_FB_ONLY = 1,
216 AFAIL_ZB_ONLY = 2,
217 AFAIL_RGB_ONLY = 3,
218 };
219
220 // GIFReg
221
222 REG64_(GIFReg, ALPHA)
223 u32 A:2;
224 u32 B:2;
225 u32 C:2;
226 u32 D:2;
227 u32 _PAD1:24;
228 u32 FIX:8;
229 u32 _PAD2:24;
230 REG_END2
231 // opaque => output will be Cs/As
232 __forceinline bool IsOpaque() const {return (A == B || C == 2 && FIX == 0) && D == 0 || (A == 0 && B == D && C == 2 && FIX == 0x80);}
233 __forceinline bool IsOpaque(int amin, int amax) const {return (A == B || amax == 0) && D == 0 || A == 0 && B == D && amin == 0x80 && amax == 0x80;}
234 REG_END2
235
236 REG64_(GIFReg, BITBLTBUF)
237 u32 SBP:14;
238 u32 _PAD1:2;
239 u32 SBW:6;
240 u32 _PAD2:2;
241 u32 SPSM:6;
242 u32 _PAD3:2;
243 u32 DBP:14;
244 u32 _PAD4:2;
245 u32 DBW:6;
246 u32 _PAD5:2;
247 u32 DPSM:6;
248 u32 _PAD6:2;
249 REG_END
250
251 REG64_(GIFReg, CLAMP)
252 union
253 {
254 struct
255 {
256 u32 WMS:2;
257 u32 WMT:2;
258 u32 MINU:10;
259 u32 MAXU:10;
260 u32 _PAD1:8;
261 u32 _PAD2:2;
262 u32 MAXV:10;
263 u32 _PAD3:20;
264 };
265
266 struct
267 {
268 u64 _PAD4:24;
269 u64 MINV:10;
270 u64 _PAD5:30;
271 };
272 };
273 REG_END
274
275 REG64_(GIFReg, COLCLAMP)
276 u32 CLAMP:1;
277 u32 _PAD1:31;
278 u32 _PAD2:32;
279 REG_END
280
281 REG64_(GIFReg, DIMX)
282 s32 DM00:3;
283 s32 _PAD00:1;
284 s32 DM01:3;
285 s32 _PAD01:1;
286 s32 DM02:3;
287 s32 _PAD02:1;
288 s32 DM03:3;
289 s32 _PAD03:1;
290 s32 DM10:3;
291 s32 _PAD10:1;
292 s32 DM11:3;
293 s32 _PAD11:1;
294 s32 DM12:3;
295 s32 _PAD12:1;
296 s32 DM13:3;
297 s32 _PAD13:1;
298 s32 DM20:3;
299 s32 _PAD20:1;
300 s32 DM21:3;
301 s32 _PAD21:1;
302 s32 DM22:3;
303 s32 _PAD22:1;
304 s32 DM23:3;
305 s32 _PAD23:1;
306 s32 DM30:3;
307 s32 _PAD30:1;
308 s32 DM31:3;
309 s32 _PAD31:1;
310 s32 DM32:3;
311 s32 _PAD32:1;
312 s32 DM33:3;
313 s32 _PAD33:1;
314 REG_END
315
316 REG64_(GIFReg, DTHE)
317 u32 DTHE:1;
318 u32 _PAD1:31;
319 u32 _PAD2:32;
320 REG_END
321
322 REG64_(GIFReg, FBA)
323 u32 FBA:1;
324 u32 _PAD1:31;
325 u32 _PAD2:32;
326 REG_END
327
328 REG64_(GIFReg, FINISH)
329 u32 _PAD1:32;
330 u32 _PAD2:32;
331 REG_END
332
333 REG64_(GIFReg, FOG)
334 u32 _PAD1:32;
335 u32 _PAD2:24;
336 u32 F:8;
337 REG_END
338
339 REG64_(GIFReg, FOGCOL)
340 u32 FCR:8;
341 u32 FCG:8;
342 u32 FCB:8;
343 u32 _PAD1:8;
344 u32 _PAD2:32;
345 REG_END
346
347 REG64_(GIFReg, FRAME)
348 u32 FBP:9;
349 u32 _PAD1:7;
350 u32 FBW:6;
351 u32 _PAD2:2;
352 u32 PSM:6;
353 u32 _PAD3:2;
354 u32 FBMSK:32;
355 REG_END2
356 u32 Block() const {return FBP << 5;}
357 REG_END2
358
359 REG64_(GIFReg, HWREG)
360 u32 DATA_LOWER:32;
361 u32 DATA_UPPER:32;
362 REG_END
363
364 REG64_(GIFReg, LABEL)
365 u32 ID:32;
366 u32 IDMSK:32;
367 REG_END
368
369 REG64_(GIFReg, MIPTBP1)
370 u64 TBP1:14;
371 u64 TBW1:6;
372 u64 TBP2:14;
373 u64 TBW2:6;
374 u64 TBP3:14;
375 u64 TBW3:6;
376 u64 _PAD:4;
377 REG_END
378
379 REG64_(GIFReg, MIPTBP2)
380 u64 TBP4:14;
381 u64 TBW4:6;
382 u64 TBP5:14;
383 u64 TBW5:6;
384 u64 TBP6:14;
385 u64 TBW6:6;
386 u64 _PAD:4;
387 REG_END
388
389 REG64_(GIFReg, NOP)
390 u32 _PAD1:32;
391 u32 _PAD2:32;
392 REG_END
393
394 REG64_(GIFReg, PABE)
395 u32 PABE:1;
396 u32 _PAD1:31;
397 u32 _PAD2:32;
398 REG_END
399
400 REG64_(GIFReg, PRIM)
401 u32 PRIM:3;
402 u32 IIP:1;
403 u32 TME:1;
404 u32 FGE:1;
405 u32 ABE:1;
406 u32 AA1:1;
407 u32 FST:1;
408 u32 CTXT:1;
409 u32 FIX:1;
410 u32 _PAD1:21;
411 u32 _PAD2:32;
412 REG_END
413
414 REG64_(GIFReg, PRMODE)
415 u32 _PRIM:3;
416 u32 IIP:1;
417 u32 TME:1;
418 u32 FGE:1;
419 u32 ABE:1;
420 u32 AA1:1;
421 u32 FST:1;
422 u32 CTXT:1;
423 u32 FIX:1;
424 u32 _PAD2:21;
425 u32 _PAD3:32;
426 REG_END
427
428 REG64_(GIFReg, PRMODECONT)
429 u32 AC:1;
430 u32 _PAD1:31;
431 u32 _PAD2:32;
432 REG_END
433
434 REG64_(GIFReg, RGBAQ)
435 u32 R:8;
436 u32 G:8;
437 u32 B:8;
438 u32 A:8;
439 float Q;
440 REG_END
441
442 REG64_(GIFReg, SCANMSK)
443 u32 MSK:2;
444 u32 _PAD1:30;
445 u32 _PAD2:32;
446 REG_END
447
448 REG64_(GIFReg, SCISSOR)
449 u32 SCAX0:11;
450 u32 _PAD1:5;
451 u32 SCAX1:11;
452 u32 _PAD2:5;
453 u32 SCAY0:11;
454 u32 _PAD3:5;
455 u32 SCAY1:11;
456 u32 _PAD4:5;
457 REG_END
458
459 REG64_(GIFReg, SIGNAL)
460 u32 ID:32;
461 u32 IDMSK:32;
462 REG_END
463
464 REG64_(GIFReg, ST)
465 float S;
466 float T;
467 REG_END
468
469 REG64_(GIFReg, TEST)
470 u32 ATE:1;
471 u32 ATST:3;
472 u32 AREF:8;
473 u32 AFAIL:2;
474 u32 DATE:1;
475 u32 DATM:1;
476 u32 ZTE:1;
477 u32 ZTST:2;
478 u32 _PAD1:13;
479 u32 _PAD2:32;
480 REG_END2
481 __forceinline bool DoFirstPass() {return !ATE || ATST != ATST_NEVER;} // not all pixels fail automatically
482 __forceinline bool DoSecondPass() {return ATE && ATST != ATST_ALWAYS && AFAIL != AFAIL_KEEP;} // pixels may fail, write fb/z
483 __forceinline bool NoSecondPass() {return ATE && ATST != ATST_ALWAYS && AFAIL == AFAIL_KEEP;} // pixels may fail, no output
484 REG_END2
485
486 REG64_(GIFReg, TEX0)
487 union
488 {
489 struct
490 {
491 u32 TBP0:14;
492 u32 TBW:6;
493 u32 PSM:6;
494 u32 TW:4;
495 u32 _PAD1:2;
496 u32 _PAD2:2;
497 u32 TCC:1;
498 u32 TFX:2;
499 u32 CBP:14;
500 u32 CPSM:4;
501 u32 CSM:1;
502 u32 CSA:5;
503 u32 CLD:3;
504 };
505
506 struct
507 {
508 u64 _PAD3:30;
509 u64 TH:4;
510 u64 _PAD4:30;
511 };
512 };
513 REG_END2
514 __forceinline bool IsRepeating() {return (u32)((u32)1 << TW) > (u32)(TBW << (u32)6);}
515 REG_END2
516
517 REG64_(GIFReg, TEX1)
518 u32 LCM:1;
519 u32 _PAD1:1;
520 u32 MXL:3;
521 u32 MMAG:1;
522 u32 MMIN:3;
523 u32 MTBA:1;
524 u32 _PAD2:9;
525 u32 L:2;
526 u32 _PAD3:11;
527 s32 K:12; // 1:7:4
528 u32 _PAD4:20;
529 REG_END2
530 bool IsMinLinear() const {return (MMIN == 1) || (MMIN & 4);}
531 bool IsMagLinear() const {return MMAG;}
532 REG_END2
533
534 REG64_(GIFReg, TEX2)
535 u32 _PAD1:20;
536 u32 PSM:6;
537 u32 _PAD2:6;
538 u32 _PAD3:5;
539 u32 CBP:14;
540 u32 CPSM:4;
541 u32 CSM:1;
542 u32 CSA:5;
543 u32 CLD:3;
544 REG_END
545
546 REG64_(GIFReg, TEXA)
547 u32 TA0:8;
548 u32 _PAD1:7;
549 u32 AEM:1;
550 u32 _PAD2:16;
551 u32 TA1:8;
552 u32 _PAD3:24;
553 REG_END
554
555 REG64_(GIFReg, TEXCLUT)
556 u32 CBW:6;
557 u32 COU:6;
558 u32 COV:10;
559 u32 _PAD1:10;
560 u32 _PAD2:32;
561 REG_END
562
563 REG64_(GIFReg, TEXFLUSH)
564 u32 _PAD1:32;
565 u32 _PAD2:32;
566 REG_END
567
568 REG64_(GIFReg, TRXDIR)
569 u32 XDIR:2;
570 u32 _PAD1:30;
571 u32 _PAD2:32;
572 REG_END
573
574 REG64_(GIFReg, TRXPOS)
575 u32 SSAX:11;
576 u32 _PAD1:5;
577 u32 SSAY:11;
578 u32 _PAD2:5;
579 u32 DSAX:11;
580 u32 _PAD3:5;
581 u32 DSAY:11;
582 u32 DIRY:1;
583 u32 DIRX:1;
584 u32 _PAD4:3;
585 REG_END
586
587 REG64_(GIFReg, TRXREG)
588 u32 RRW:12;
589 u32 _PAD1:20;
590 u32 RRH:12;
591 u32 _PAD2:20;
592 REG_END
593
594 REG64_(GIFReg, UV)
595 u32 U:14;
596 u32 _PAD1:2;
597 u32 V:14;
598 u32 _PAD2:2;
599 u32 _PAD3:32;
600 REG_END
601
602 REG64_(GIFReg, XYOFFSET)
603 u32 OFX:16;
604 u32 _PAD1:16;
605 u32 OFY:16;
606 u32 _PAD2:16;
607 REG_END
608
609 REG64_(GIFReg, XYZ)
610 u32 X:16;
611 u32 Y:16;
612 u32 Z:32;
613 REG_END
614
615 REG64_(GIFReg, XYZF)
616 u32 X:16;
617 u32 Y:16;
618 u32 Z:24;
619 u32 F:8;
620 REG_END
621
622 REG64_(GIFReg, ZBUF)
623 u32 ZBP:9;
624 u32 _PAD1:15;
625 // u32 PSM:4;
626 // u32 _PAD2:4;
627 u32 PSM:6;
628 u32 _PAD2:2;
629 u32 ZMSK:1;
630 u32 _PAD3:31;
631 REG_END2
632 u32 Block() const {return ZBP << 5;}
633 REG_END2
634
635 REG64_SET(GIFReg)
636 GIFRegALPHA ALPHA;
637 GIFRegBITBLTBUF BITBLTBUF;
638 GIFRegCLAMP CLAMP;
639 GIFRegCOLCLAMP COLCLAMP;
640 GIFRegDIMX DIMX;
641 GIFRegDTHE DTHE;
642 GIFRegFBA FBA;
643 GIFRegFINISH FINISH;
644 GIFRegFOG FOG;
645 GIFRegFOGCOL FOGCOL;
646 GIFRegFRAME FRAME;
647 GIFRegHWREG HWREG;
648 GIFRegLABEL LABEL;
649 GIFRegMIPTBP1 MIPTBP1;
650 GIFRegMIPTBP2 MIPTBP2;
651 GIFRegNOP NOP;
652 GIFRegPABE PABE;
653 GIFRegPRIM PRIM;
654 GIFRegPRMODE PRMODE;
655 GIFRegPRMODECONT PRMODECONT;
656 GIFRegRGBAQ RGBAQ;
657 GIFRegSCANMSK SCANMSK;
658 GIFRegSCISSOR SCISSOR;
659 GIFRegSIGNAL SIGNAL;
660 GIFRegST ST;
661 GIFRegTEST TEST;
662 GIFRegTEX0 TEX0;
663 GIFRegTEX1 TEX1;
664 GIFRegTEX2 TEX2;
665 GIFRegTEXA TEXA;
666 GIFRegTEXCLUT TEXCLUT;
667 GIFRegTEXFLUSH TEXFLUSH;
668 GIFRegTRXDIR TRXDIR;
669 GIFRegTRXPOS TRXPOS;
670 GIFRegTRXREG TRXREG;
671 GIFRegUV UV;
672 GIFRegXYOFFSET XYOFFSET;
673 GIFRegXYZ XYZ;
674 GIFRegXYZF XYZF;
675 GIFRegZBUF ZBUF;
676 REG_SET_END
677
678 // GIFPacked
679
680 REG128_(GIFPacked, PRIM)
681 u32 PRIM:11;
682 u32 _PAD1:21;
683 u32 _PAD2:32;
684 u32 _PAD3:32;
685 u32 _PAD4:32;
686 REG_END
687
688 REG128_(GIFPacked, RGBA)
689 u32 R:8;
690 u32 _PAD1:24;
691 u32 G:8;
692 u32 _PAD2:24;
693 u32 B:8;
694 u32 _PAD3:24;
695 u32 A:8;
696 u32 _PAD4:24;
697 REG_END
698
699 REG128_(GIFPacked, STQ)
700 float S;
701 float T;
702 float Q;
703 u32 _PAD1:32;
704 REG_END
705
706 REG128_(GIFPacked, UV)
707 u32 U:14;
708 u32 _PAD1:18;
709 u32 V:14;
710 u32 _PAD2:18;
711 u32 _PAD3:32;
712 u32 _PAD4:32;
713 REG_END
714
715 REG128_(GIFPacked, XYZF2)
716 u32 X:16;
717 u32 _PAD1:16;
718 u32 Y:16;
719 u32 _PAD2:16;
720 u32 _PAD3:4;
721 u32 Z:24;
722 u32 _PAD4:4;
723 u32 _PAD5:4;
724 u32 F:8;
725 u32 _PAD6:3;
726 u32 ADC:1;
727 u32 _PAD7:16;
728 REG_END
729
730 REG128_(GIFPacked, XYZ2)
731 u32 X:16;
732 u32 _PAD1:16;
733 u32 Y:16;
734 u32 _PAD2:16;
735 u32 Z:32;
736 u32 _PAD3:15;
737 u32 ADC:1;
738 u32 _PAD4:16;
739 REG_END
740
741 REG128_(GIFPacked, FOG)
742 u32 _PAD1:32;
743 u32 _PAD2:32;
744 u32 _PAD3:32;
745 u32 _PAD4:4;
746 u32 F:8;
747 u32 _PAD5:20;
748 REG_END
749
750 REG128_(GIFPacked, A_D)
751 u64 DATA:64;
752 u32 ADDR:8; // enum GIF_A_D_REG
753 u32 _PAD1:24;
754 u32 _PAD2:32;
755 REG_END
756
757 REG128_(GIFPacked, NOP)
758 u32 _PAD1:32;
759 u32 _PAD2:32;
760 u32 _PAD3:32;
761 u32 _PAD4:32;
762 REG_END
763
764 REG128_SET(GIFPackedReg)
765 GIFReg r;
766 GIFPackedPRIM PRIM;
767 GIFPackedRGBA RGBA;
768 GIFPackedSTQ STQ;
769 GIFPackedUV UV;
770 GIFPackedXYZF2 XYZF2;
771 GIFPackedXYZ2 XYZ2;
772 GIFPackedFOG FOG;
773 GIFPackedA_D A_D;
774 GIFPackedNOP NOP;
775 REG_SET_END
776
777 REG64_(GSReg, BGCOLOR)
778 u32 R:8;
779 u32 G:8;
780 u32 B:8;
781 u32 _PAD1:8;
782 u32 _PAD2:32;
783 REG_END
784
785 REG64_(GSReg, BUSDIR)
786 u32 DIR:1;
787 u32 _PAD1:31;
788 u32 _PAD2:32;
789 REG_END
790
791 REG64_(GSReg, CSR)
792 u32 SIGNAL:1;
793 u32 FINISH:1;
794 u32 HSINT:1;
795 u32 VSINT:1;
796 u32 EDWINT:1;
797 u32 ZERO1:1;
798 u32 ZERO2:1;
799 u32 _PAD1:1;
800 u32 FLUSH:1;
801 u32 RESET:1;
802 u32 _PAD2:2;
803 u32 NFIELD:1;
804 u32 FIELD:1;
805 u32 FIFO:2;
806 u32 REV:8;
807 u32 ID:8;
808 u32 _PAD3:32;
809 REG_END
810
811 REG64_(GSReg, DISPFB) // (-1/2)
812 u32 FBP:9;
813 u32 FBW:6;
814 u32 PSM:5;
815 u32 _PAD:12;
816 u32 DBX:11;
817 u32 DBY:11;
818 u32 _PAD2:10;
819 REG_END
820
821 REG64_(GSReg, DISPLAY) // (-1/2)
822 u32 DX:12;
823 u32 DY:11;
824 u32 MAGH:4;
825 u32 MAGV:2;
826 u32 _PAD:3;
827 u32 DW:12;
828 u32 DH:11;
829 u32 _PAD2:9;
830 REG_END
831
832 REG64_(GSReg, EXTBUF)
833 u32 EXBP:14;
834 u32 EXBW:6;
835 u32 FBIN:2;
836 u32 WFFMD:1;
837 u32 EMODA:2;
838 u32 EMODC:2;
839 u32 _PAD1:5;
840 u32 WDX:11;
841 u32 WDY:11;
842 u32 _PAD2:10;
843 REG_END
844
845 REG64_(GSReg, EXTDATA)
846 u32 SX:12;
847 u32 SY:11;
848 u32 SMPH:4;
849 u32 SMPV:2;
850 u32 _PAD1:3;
851 u32 WW:12;
852 u32 WH:11;
853 u32 _PAD2:9;
854 REG_END
855
856 REG64_(GSReg, EXTWRITE)
857 u32 WRITE;
858 u32 _PAD2:32;
859 REG_END
860
861 REG64_(GSReg, IMR)
862 u32 _PAD1:8;
863 u32 SIGMSK:1;
864 u32 FINISHMSK:1;
865 u32 HSMSK:1;
866 u32 VSMSK:1;
867 u32 EDWMSK:1;
868 u32 _PAD2:19;
869 u32 _PAD3:32;
870 REG_END
871
872 REG64_(GSReg, PMODE)
873 u32 EN1:1;
874 u32 EN2:1;
875 u32 CRTMD:3;
876 u32 MMOD:1;
877 u32 AMOD:1;
878 u32 SLBG:1;
879 u32 ALP:8;
880 u32 _PAD:16;
881 u32 _PAD1:32;
882 REG_END
883
884 REG64_(GSReg, SIGLBLID)
885 u32 SIGID:32;
886 u32 LBLID:32;
887 REG_END
888
889 REG64_(GSReg, SMODE1)
890 u32 RC:3;
891 u32 LC:7;
892 u32 T1248:2;
893 u32 SLCK:1;
894 u32 CMOD:2;
895 u32 EX:1;
896 u32 PRST:1;
897 u32 SINT:1;
898 u32 XPCK:1;
899 u32 PCK2:2;
900 u32 SPML:4;
901 u32 GCONT:1;
902 u32 PHS:1;
903 u32 PVS:1;
904 u32 PEHS:1;
905 u32 PEVS:1;
906 u32 CLKSEL:2;
907 u32 NVCK:1;
908 u32 SLCK2:1;
909 u32 VCKSEL:2;
910 u32 VHP:1;
911 u32 _PAD1:27;
912 REG_END
913
914 REG64_(GSReg, SMODE2)
915 u32 INT:1;
916 u32 FFMD:1;
917 u32 DPMS:2;
918 u32 _PAD2:28;
919 u32 _PAD3:32;
920 REG_END
921
922 REG64_(GSReg, SIGBLID)
923 u32 SIGID;
924 u32 LBLID;
925 REG_END
926
927 #define PMODE ((GSRegPMODE*)(g_pBasePS2Mem+0x0000))
928 #define SMODE1 ((GSRegSMODE1*)(g_pBasePS2Mem+0x0010))
929 #define SMODE2 ((GSRegSMODE2*)(g_pBasePS2Mem+0x0020))
930 // SRFSH
931 #define SYNCH1 ((GSRegSYNCH1*)(g_pBasePS2Mem+0x0040))
932 #define SYNCH2 ((GSRegSYNCH2*)(g_pBasePS2Mem+0x0050))
933 #define SYNCV ((GSRegSYNCV*)(g_pBasePS2Mem+0x0060))
934 #define DISPFB1 ((GSRegDISPFB*)(g_pBasePS2Mem+0x0070))
935 #define DISPLAY1 ((GSRegDISPLAY*)(g_pBasePS2Mem+0x0080))
936 #define DISPFB2 ((GSRegDISPFB*)(g_pBasePS2Mem+0x0090))
937 #define DISPLAY2 ((GSRegDISPLAY*)(g_pBasePS2Mem+0x00a0))
938 #define EXTBUF ((GSRegEXTBUF*)(g_pBasePS2Mem+0x00b0))
939 #define EXTDATA ((GSRegEXTDATA*)(g_pBasePS2Mem+0x00c0))
940 #define EXTWRITE ((GSRegEXTWRITE*)(g_pBasePS2Mem+0x00d0))
941 #define BGCOLOR ((GSRegBGCOLOR*)(g_pBasePS2Mem+0x00e0))
942 #define CSR ((GSRegCSR*)(g_pBasePS2Mem+0x1000))
943 #define IMR ((GSRegIMR*)(g_pBasePS2Mem+0x1010))
944 #define BUSDIR ((GSRegBUSDIR*)(g_pBasePS2Mem+0x1040))
945 #define SIGLBLID ((GSRegSIGBLID*)(g_pBasePS2Mem+0x1080))
946
947 //
948 // sps2tags.h
949 //
950 #define GET_GIF_REG(tag, reg) \
951 (((tag).ai32[2 + ((reg) >> 3)] >> (((reg) & 7) << 2)) & 0xf)
952
953 #define GET_GSFPS (((SMODE1->CMOD&1) ? 50 : 60) / (SMODE2->INT ? 1 : 2))
954
955 extern void WriteTempRegs();
956 extern void SetFrameSkip(bool skip);
957 extern void ResetRegs();
958
959 extern void SetTexFlush();
960 extern void SetFogColor(u32 fog);
961 extern void SetFogColor(GIFRegFOGCOL* fog);
962 extern bool CheckChangeInClut(u32 highdword, u32 psm); // returns true if clut will change after this tex0 op
963
964 // flush current vertices, call before setting new registers (the main render method)
965 void Flush(int context);
966 void FlushBoth();
967
968 // called on a primitive switch
969 void Prim();
970
971 #endif
972
973 #endif // NEWREGS_H_INCLUDED

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